AT91SAM7S64.h
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042 #ifndef AT91SAM7S64_H
00043 #define AT91SAM7S64_H
00044
00045 typedef volatile unsigned int AT91_REG;
00046
00047
00048
00049
00050 typedef struct _AT91S_SYS {
00051 AT91_REG AIC_SMR[32];
00052 AT91_REG AIC_SVR[32];
00053 AT91_REG AIC_IVR;
00054 AT91_REG AIC_FVR;
00055 AT91_REG AIC_ISR;
00056 AT91_REG AIC_IPR;
00057 AT91_REG AIC_IMR;
00058 AT91_REG AIC_CISR;
00059 AT91_REG Reserved0[2];
00060 AT91_REG AIC_IECR;
00061 AT91_REG AIC_IDCR;
00062 AT91_REG AIC_ICCR;
00063 AT91_REG AIC_ISCR;
00064 AT91_REG AIC_EOICR;
00065 AT91_REG AIC_SPU;
00066 AT91_REG AIC_DCR;
00067 AT91_REG Reserved1[1];
00068 AT91_REG AIC_FFER;
00069 AT91_REG AIC_FFDR;
00070 AT91_REG AIC_FFSR;
00071 AT91_REG Reserved2[45];
00072 AT91_REG DBGU_CR;
00073 AT91_REG DBGU_MR;
00074 AT91_REG DBGU_IER;
00075 AT91_REG DBGU_IDR;
00076 AT91_REG DBGU_IMR;
00077 AT91_REG DBGU_CSR;
00078 AT91_REG DBGU_RHR;
00079 AT91_REG DBGU_THR;
00080 AT91_REG DBGU_BRGR;
00081 AT91_REG Reserved3[7];
00082 AT91_REG DBGU_CIDR;
00083 AT91_REG DBGU_EXID;
00084 AT91_REG DBGU_FNTR;
00085 AT91_REG Reserved4[45];
00086 AT91_REG DBGU_RPR;
00087 AT91_REG DBGU_RCR;
00088 AT91_REG DBGU_TPR;
00089 AT91_REG DBGU_TCR;
00090 AT91_REG DBGU_RNPR;
00091 AT91_REG DBGU_RNCR;
00092 AT91_REG DBGU_TNPR;
00093 AT91_REG DBGU_TNCR;
00094 AT91_REG DBGU_PTCR;
00095 AT91_REG DBGU_PTSR;
00096 AT91_REG Reserved5[54];
00097 AT91_REG PIOA_PER;
00098 AT91_REG PIOA_PDR;
00099 AT91_REG PIOA_PSR;
00100 AT91_REG Reserved6[1];
00101 AT91_REG PIOA_OER;
00102 AT91_REG PIOA_ODR;
00103 AT91_REG PIOA_OSR;
00104 AT91_REG Reserved7[1];
00105 AT91_REG PIOA_IFER;
00106 AT91_REG PIOA_IFDR;
00107 AT91_REG PIOA_IFSR;
00108 AT91_REG Reserved8[1];
00109 AT91_REG PIOA_SODR;
00110 AT91_REG PIOA_CODR;
00111 AT91_REG PIOA_ODSR;
00112 AT91_REG PIOA_PDSR;
00113 AT91_REG PIOA_IER;
00114 AT91_REG PIOA_IDR;
00115 AT91_REG PIOA_IMR;
00116 AT91_REG PIOA_ISR;
00117 AT91_REG PIOA_MDER;
00118 AT91_REG PIOA_MDDR;
00119 AT91_REG PIOA_MDSR;
00120 AT91_REG Reserved9[1];
00121 AT91_REG PIOA_PPUDR;
00122 AT91_REG PIOA_PPUER;
00123 AT91_REG PIOA_PPUSR;
00124 AT91_REG Reserved10[1];
00125 AT91_REG PIOA_ASR;
00126 AT91_REG PIOA_BSR;
00127 AT91_REG PIOA_ABSR;
00128 AT91_REG Reserved11[9];
00129 AT91_REG PIOA_OWER;
00130 AT91_REG PIOA_OWDR;
00131 AT91_REG PIOA_OWSR;
00132 AT91_REG Reserved12[469];
00133 AT91_REG PMC_SCER;
00134 AT91_REG PMC_SCDR;
00135 AT91_REG PMC_SCSR;
00136 AT91_REG Reserved13[1];
00137 AT91_REG PMC_PCER;
00138 AT91_REG PMC_PCDR;
00139 AT91_REG PMC_PCSR;
00140 AT91_REG Reserved14[1];
00141 AT91_REG PMC_MOR;
00142 AT91_REG PMC_MCFR;
00143 AT91_REG Reserved15[1];
00144 AT91_REG PMC_PLLR;
00145 AT91_REG PMC_MCKR;
00146 AT91_REG Reserved16[3];
00147 AT91_REG PMC_PCKR[3];
00148 AT91_REG Reserved17[5];
00149 AT91_REG PMC_IER;
00150 AT91_REG PMC_IDR;
00151 AT91_REG PMC_SR;
00152 AT91_REG PMC_IMR;
00153 AT91_REG Reserved18[36];
00154 AT91_REG RSTC_RCR;
00155 AT91_REG RSTC_RSR;
00156 AT91_REG RSTC_RMR;
00157 AT91_REG Reserved19[5];
00158 AT91_REG RTTC_RTMR;
00159 AT91_REG RTTC_RTAR;
00160 AT91_REG RTTC_RTVR;
00161 AT91_REG RTTC_RTSR;
00162 AT91_REG PITC_PIMR;
00163 AT91_REG PITC_PISR;
00164 AT91_REG PITC_PIVR;
00165 AT91_REG PITC_PIIR;
00166 AT91_REG WDTC_WDCR;
00167 AT91_REG WDTC_WDMR;
00168 AT91_REG WDTC_WDSR;
00169 AT91_REG Reserved20[5];
00170 AT91_REG VREG_MR;
00171 } AT91S_SYS, *AT91PS_SYS;
00172
00173
00174
00175
00176
00177 typedef struct _AT91S_AIC {
00178 AT91_REG AIC_SMR[32];
00179 AT91_REG AIC_SVR[32];
00180 AT91_REG AIC_IVR;
00181 AT91_REG AIC_FVR;
00182 AT91_REG AIC_ISR;
00183 AT91_REG AIC_IPR;
00184 AT91_REG AIC_IMR;
00185 AT91_REG AIC_CISR;
00186 AT91_REG Reserved0[2];
00187 AT91_REG AIC_IECR;
00188 AT91_REG AIC_IDCR;
00189 AT91_REG AIC_ICCR;
00190 AT91_REG AIC_ISCR;
00191 AT91_REG AIC_EOICR;
00192 AT91_REG AIC_SPU;
00193 AT91_REG AIC_DCR;
00194 AT91_REG Reserved1[1];
00195 AT91_REG AIC_FFER;
00196 AT91_REG AIC_FFDR;
00197 AT91_REG AIC_FFSR;
00198 } AT91S_AIC, *AT91PS_AIC;
00199
00200
00201 #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
00202 #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
00203 #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
00204 #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
00205 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
00206 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
00207 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
00208 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
00209
00210 #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
00211 #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
00212
00213 #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
00214 #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
00215
00216
00217
00218
00219 typedef struct _AT91S_PDC {
00220 AT91_REG PDC_RPR;
00221 AT91_REG PDC_RCR;
00222 AT91_REG PDC_TPR;
00223 AT91_REG PDC_TCR;
00224 AT91_REG PDC_RNPR;
00225 AT91_REG PDC_RNCR;
00226 AT91_REG PDC_TNPR;
00227 AT91_REG PDC_TNCR;
00228 AT91_REG PDC_PTCR;
00229 AT91_REG PDC_PTSR;
00230 } AT91S_PDC, *AT91PS_PDC;
00231
00232
00233 #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
00234 #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
00235 #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
00236 #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
00237
00238
00239
00240
00241
00242 typedef struct _AT91S_DBGU {
00243 AT91_REG DBGU_CR;
00244 AT91_REG DBGU_MR;
00245 AT91_REG DBGU_IER;
00246 AT91_REG DBGU_IDR;
00247 AT91_REG DBGU_IMR;
00248 AT91_REG DBGU_CSR;
00249 AT91_REG DBGU_RHR;
00250 AT91_REG DBGU_THR;
00251 AT91_REG DBGU_BRGR;
00252 AT91_REG Reserved0[7];
00253 AT91_REG DBGU_CIDR;
00254 AT91_REG DBGU_EXID;
00255 AT91_REG DBGU_FNTR;
00256 AT91_REG Reserved1[45];
00257 AT91_REG DBGU_RPR;
00258 AT91_REG DBGU_RCR;
00259 AT91_REG DBGU_TPR;
00260 AT91_REG DBGU_TCR;
00261 AT91_REG DBGU_RNPR;
00262 AT91_REG DBGU_RNCR;
00263 AT91_REG DBGU_TNPR;
00264 AT91_REG DBGU_TNCR;
00265 AT91_REG DBGU_PTCR;
00266 AT91_REG DBGU_PTSR;
00267 } AT91S_DBGU, *AT91PS_DBGU;
00268
00269
00270 #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
00271 #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
00272 #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
00273 #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
00274 #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
00275 #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
00276 #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
00277
00278 #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
00279 #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
00280 #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
00281 #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
00282 #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
00283 #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
00284 #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
00285 #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
00286 #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
00287 #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
00288 #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
00289 #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
00290
00291 #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
00292 #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
00293 #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
00294 #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
00295 #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
00296 #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
00297 #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
00298 #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
00299 #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
00300 #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
00301 #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
00302 #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
00303
00304
00305
00306
00307 #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
00308
00309
00310
00311
00312 typedef struct _AT91S_PIO {
00313 AT91_REG PIO_PER;
00314 AT91_REG PIO_PDR;
00315 AT91_REG PIO_PSR;
00316 AT91_REG Reserved0[1];
00317 AT91_REG PIO_OER;
00318 AT91_REG PIO_ODR;
00319 AT91_REG PIO_OSR;
00320 AT91_REG Reserved1[1];
00321 AT91_REG PIO_IFER;
00322 AT91_REG PIO_IFDR;
00323 AT91_REG PIO_IFSR;
00324 AT91_REG Reserved2[1];
00325 AT91_REG PIO_SODR;
00326 AT91_REG PIO_CODR;
00327 AT91_REG PIO_ODSR;
00328 AT91_REG PIO_PDSR;
00329 AT91_REG PIO_IER;
00330 AT91_REG PIO_IDR;
00331 AT91_REG PIO_IMR;
00332 AT91_REG PIO_ISR;
00333 AT91_REG PIO_MDER;
00334 AT91_REG PIO_MDDR;
00335 AT91_REG PIO_MDSR;
00336 AT91_REG Reserved3[1];
00337 AT91_REG PIO_PPUDR;
00338 AT91_REG PIO_PPUER;
00339 AT91_REG PIO_PPUSR;
00340 AT91_REG Reserved4[1];
00341 AT91_REG PIO_ASR;
00342 AT91_REG PIO_BSR;
00343 AT91_REG PIO_ABSR;
00344 AT91_REG Reserved5[9];
00345 AT91_REG PIO_OWER;
00346 AT91_REG PIO_OWDR;
00347 AT91_REG PIO_OWSR;
00348 } AT91S_PIO, *AT91PS_PIO;
00349
00350
00351
00352
00353
00354 typedef struct _AT91S_CKGR {
00355 AT91_REG CKGR_MOR;
00356 AT91_REG CKGR_MCFR;
00357 AT91_REG Reserved0[1];
00358 AT91_REG CKGR_PLLR;
00359 } AT91S_CKGR, *AT91PS_CKGR;
00360
00361
00362 #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
00363 #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
00364 #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
00365
00366 #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
00367 #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
00368
00369 #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
00370 #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
00371 #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
00372 #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
00373 #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
00374 #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
00375 #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
00376 #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
00377 #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
00378 #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
00379 #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
00380 #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
00381 #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
00382 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
00383
00384
00385
00386
00387 typedef struct _AT91S_PMC {
00388 AT91_REG PMC_SCER;
00389 AT91_REG PMC_SCDR;
00390 AT91_REG PMC_SCSR;
00391 AT91_REG Reserved0[1];
00392 AT91_REG PMC_PCER;
00393 AT91_REG PMC_PCDR;
00394 AT91_REG PMC_PCSR;
00395 AT91_REG Reserved1[1];
00396 AT91_REG PMC_MOR;
00397 AT91_REG PMC_MCFR;
00398 AT91_REG Reserved2[1];
00399 AT91_REG PMC_PLLR;
00400 AT91_REG PMC_MCKR;
00401 AT91_REG Reserved3[3];
00402 AT91_REG PMC_PCKR[3];
00403 AT91_REG Reserved4[5];
00404 AT91_REG PMC_IER;
00405 AT91_REG PMC_IDR;
00406 AT91_REG PMC_SR;
00407 AT91_REG PMC_IMR;
00408 } AT91S_PMC, *AT91PS_PMC;
00409
00410
00411 #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
00412 #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
00413 #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
00414 #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
00415 #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
00416
00417
00418
00419
00420
00421
00422 #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
00423 #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
00424 #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
00425 #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
00426 #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
00427 #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
00428 #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
00429 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
00430 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
00431 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
00432 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
00433 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
00434
00435
00436 #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
00437 #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
00438 #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
00439 #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
00440 #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
00441 #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
00442
00443
00444
00445
00446
00447
00448
00449 typedef struct _AT91S_RSTC {
00450 AT91_REG RSTC_RCR;
00451 AT91_REG RSTC_RSR;
00452 AT91_REG RSTC_RMR;
00453 } AT91S_RSTC, *AT91PS_RSTC;
00454
00455
00456 #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
00457 #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
00458 #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
00459 #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
00460
00461 #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
00462 #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
00463 #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
00464 #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
00465 #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
00466 #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
00467 #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
00468 #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
00469 #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
00470 #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
00471 #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
00472
00473 #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
00474 #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
00475 #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
00476 #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
00477
00478
00479
00480
00481 typedef struct _AT91S_RTTC {
00482 AT91_REG RTTC_RTMR;
00483 AT91_REG RTTC_RTAR;
00484 AT91_REG RTTC_RTVR;
00485 AT91_REG RTTC_RTSR;
00486 } AT91S_RTTC, *AT91PS_RTTC;
00487
00488
00489 #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
00490 #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
00491 #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
00492 #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
00493
00494 #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
00495
00496 #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
00497
00498 #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
00499 #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
00500
00501
00502
00503
00504 typedef struct _AT91S_PITC {
00505 AT91_REG PITC_PIMR;
00506 AT91_REG PITC_PISR;
00507 AT91_REG PITC_PIVR;
00508 AT91_REG PITC_PIIR;
00509 } AT91S_PITC, *AT91PS_PITC;
00510
00511
00512 #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
00513 #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
00514 #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
00515
00516 #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
00517
00518 #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
00519 #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
00520
00521
00522
00523
00524
00525 typedef struct _AT91S_WDTC {
00526 AT91_REG WDTC_WDCR;
00527 AT91_REG WDTC_WDMR;
00528 AT91_REG WDTC_WDSR;
00529 } AT91S_WDTC, *AT91PS_WDTC;
00530
00531
00532 #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
00533 #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
00534
00535 #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
00536 #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
00537 #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
00538 #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
00539 #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
00540 #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
00541 #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
00542 #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
00543
00544 #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
00545 #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
00546
00547
00548
00549
00550 typedef struct _AT91S_VREG {
00551 AT91_REG VREG_MR;
00552 } AT91S_VREG, *AT91PS_VREG;
00553
00554
00555 #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
00556
00557
00558
00559
00560 typedef struct _AT91S_MC {
00561 AT91_REG MC_RCR;
00562 AT91_REG MC_ASR;
00563 AT91_REG MC_AASR;
00564 AT91_REG Reserved0[21];
00565 AT91_REG MC_FMR;
00566 AT91_REG MC_FCR;
00567 AT91_REG MC_FSR;
00568 } AT91S_MC, *AT91PS_MC;
00569
00570
00571 #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
00572
00573 #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
00574 #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
00575 #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
00576 #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
00577 #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
00578 #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
00579 #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
00580 #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
00581 #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
00582 #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
00583 #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
00584 #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
00585 #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
00586 #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
00587
00588 #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
00589 #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
00590 #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
00591 #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
00592 #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
00593 #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
00594 #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
00595 #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
00596 #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
00597 #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
00598
00599 #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
00600 #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
00601 #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
00602 #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
00603 #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
00604 #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
00605 #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
00606 #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
00607 #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
00608 #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
00609 #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
00610
00611 #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
00612 #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
00613 #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
00614 #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
00615 #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
00616 #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
00617 #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
00618 #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
00619 #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
00620 #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
00621 #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
00622 #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
00623 #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
00624 #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
00625 #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
00626 #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
00627 #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
00628 #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
00629 #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
00630 #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
00631 #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
00632 #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
00633 #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
00634 #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
00635 #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
00636
00637
00638
00639
00640 typedef struct _AT91S_SPI {
00641 AT91_REG SPI_CR;
00642 AT91_REG SPI_MR;
00643 AT91_REG SPI_RDR;
00644 AT91_REG SPI_TDR;
00645 AT91_REG SPI_SR;
00646 AT91_REG SPI_IER;
00647 AT91_REG SPI_IDR;
00648 AT91_REG SPI_IMR;
00649 AT91_REG Reserved0[4];
00650 AT91_REG SPI_CSR[4];
00651 AT91_REG Reserved1[48];
00652 AT91_REG SPI_RPR;
00653 AT91_REG SPI_RCR;
00654 AT91_REG SPI_TPR;
00655 AT91_REG SPI_TCR;
00656 AT91_REG SPI_RNPR;
00657 AT91_REG SPI_RNCR;
00658 AT91_REG SPI_TNPR;
00659 AT91_REG SPI_TNCR;
00660 AT91_REG SPI_PTCR;
00661 AT91_REG SPI_PTSR;
00662 } AT91S_SPI, *AT91PS_SPI;
00663
00664
00665 #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
00666 #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
00667 #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
00668 #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
00669
00670 #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
00671 #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
00672 #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
00673 #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
00674 #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
00675 #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
00676 #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
00677 #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
00678 #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
00679 #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
00680
00681 #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
00682 #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
00683
00684 #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
00685 #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
00686
00687 #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
00688 #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
00689 #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
00690 #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
00691 #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
00692 #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
00693 #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
00694 #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
00695 #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
00696 #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
00697 #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
00698
00699
00700
00701
00702 #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
00703 #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
00704 #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
00705 #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
00706 #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
00707 #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
00708 #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
00709 #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
00710 #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
00711 #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
00712 #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
00713 #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
00714 #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
00715 #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
00716 #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
00717 #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
00718
00719
00720
00721
00722 typedef struct _AT91S_ADC {
00723 AT91_REG ADC_CR;
00724 AT91_REG ADC_MR;
00725 AT91_REG Reserved0[2];
00726 AT91_REG ADC_CHER;
00727 AT91_REG ADC_CHDR;
00728 AT91_REG ADC_CHSR;
00729 AT91_REG ADC_SR;
00730 AT91_REG ADC_LCDR;
00731 AT91_REG ADC_IER;
00732 AT91_REG ADC_IDR;
00733 AT91_REG ADC_IMR;
00734 AT91_REG ADC_CDR0;
00735 AT91_REG ADC_CDR1;
00736 AT91_REG ADC_CDR2;
00737 AT91_REG ADC_CDR3;
00738 AT91_REG ADC_CDR4;
00739 AT91_REG ADC_CDR5;
00740 AT91_REG ADC_CDR6;
00741 AT91_REG ADC_CDR7;
00742 AT91_REG Reserved1[44];
00743 AT91_REG ADC_RPR;
00744 AT91_REG ADC_RCR;
00745 AT91_REG ADC_TPR;
00746 AT91_REG ADC_TCR;
00747 AT91_REG ADC_RNPR;
00748 AT91_REG ADC_RNCR;
00749 AT91_REG ADC_TNPR;
00750 AT91_REG ADC_TNCR;
00751 AT91_REG ADC_PTCR;
00752 AT91_REG ADC_PTSR;
00753 } AT91S_ADC, *AT91PS_ADC;
00754
00755
00756 #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
00757 #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
00758
00759 #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
00760 #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
00761 #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
00762 #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
00763 #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
00764 #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
00765 #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
00766 #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
00767 #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
00768 #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
00769 #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
00770 #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
00771 #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
00772 #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
00773 #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
00774 #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
00775 #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
00776 #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
00777 #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
00778 #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
00779
00780 #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
00781 #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
00782 #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
00783 #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
00784 #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
00785 #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
00786 #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
00787 #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
00788
00789
00790
00791 #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
00792 #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
00793 #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
00794 #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
00795 #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
00796 #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
00797 #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
00798 #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
00799 #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
00800 #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
00801 #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
00802 #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
00803 #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
00804 #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
00805 #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
00806 #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
00807 #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
00808 #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
00809 #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
00810 #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
00811
00812 #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
00813
00814
00815
00816
00817 #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
00818
00819
00820
00821
00822
00823
00824
00825
00826
00827
00828
00829 typedef struct _AT91S_SSC {
00830 AT91_REG SSC_CR;
00831 AT91_REG SSC_CMR;
00832 AT91_REG Reserved0[2];
00833 AT91_REG SSC_RCMR;
00834 AT91_REG SSC_RFMR;
00835 AT91_REG SSC_TCMR;
00836 AT91_REG SSC_TFMR;
00837 AT91_REG SSC_RHR;
00838 AT91_REG SSC_THR;
00839 AT91_REG Reserved1[2];
00840 AT91_REG SSC_RSHR;
00841 AT91_REG SSC_TSHR;
00842 AT91_REG Reserved2[2];
00843 AT91_REG SSC_SR;
00844 AT91_REG SSC_IER;
00845 AT91_REG SSC_IDR;
00846 AT91_REG SSC_IMR;
00847 AT91_REG Reserved3[44];
00848 AT91_REG SSC_RPR;
00849 AT91_REG SSC_RCR;
00850 AT91_REG SSC_TPR;
00851 AT91_REG SSC_TCR;
00852 AT91_REG SSC_RNPR;
00853 AT91_REG SSC_RNCR;
00854 AT91_REG SSC_TNPR;
00855 AT91_REG SSC_TNCR;
00856 AT91_REG SSC_PTCR;
00857 AT91_REG SSC_PTSR;
00858 } AT91S_SSC, *AT91PS_SSC;
00859
00860
00861 #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
00862 #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
00863 #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
00864 #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
00865 #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
00866
00867 #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
00868 #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
00869 #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
00870 #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
00871 #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
00872 #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
00873 #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
00874 #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
00875 #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
00876 #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
00877 #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
00878 #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
00879 #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
00880 #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
00881 #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
00882 #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
00883 #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
00884 #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
00885 #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
00886 #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
00887 #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
00888
00889 #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
00890 #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
00891 #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
00892 #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
00893 #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
00894 #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
00895 #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
00896 #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
00897 #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
00898 #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
00899 #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
00900 #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
00901 #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
00902
00903
00904 #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
00905 #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
00906
00907 #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
00908 #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
00909 #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
00910 #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
00911 #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
00912 #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
00913 #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
00914 #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
00915 #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
00916 #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
00917 #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
00918 #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
00919
00920
00921
00922
00923
00924
00925
00926 typedef struct _AT91S_USART {
00927 AT91_REG US_CR;
00928 AT91_REG US_MR;
00929 AT91_REG US_IER;
00930 AT91_REG US_IDR;
00931 AT91_REG US_IMR;
00932 AT91_REG US_CSR;
00933 AT91_REG US_RHR;
00934 AT91_REG US_THR;
00935 AT91_REG US_BRGR;
00936 AT91_REG US_RTOR;
00937 AT91_REG US_TTGR;
00938 AT91_REG Reserved0[5];
00939 AT91_REG US_FIDI;
00940 AT91_REG US_NER;
00941 AT91_REG Reserved1[1];
00942 AT91_REG US_IF;
00943 AT91_REG Reserved2[44];
00944 AT91_REG US_RPR;
00945 AT91_REG US_RCR;
00946 AT91_REG US_TPR;
00947 AT91_REG US_TCR;
00948 AT91_REG US_RNPR;
00949 AT91_REG US_RNCR;
00950 AT91_REG US_TNPR;
00951 AT91_REG US_TNCR;
00952 AT91_REG US_PTCR;
00953 AT91_REG US_PTSR;
00954 } AT91S_USART, *AT91PS_USART;
00955
00956
00957 #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
00958 #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
00959 #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
00960 #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
00961 #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
00962 #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
00963 #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
00964 #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
00965 #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
00966 #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
00967 #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
00968
00969 #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
00970 #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
00971 #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
00972 #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
00973 #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
00974 #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
00975 #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
00976 #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
00977 #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
00978 #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
00979 #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
00980 #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
00981 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
00982 #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
00983 #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
00984 #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
00985 #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
00986 #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
00987 #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
00988 #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
00989 #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
00990 #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
00991 #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
00992 #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
00993 #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
00994 #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
00995 #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
00996 #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
00997 #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
00998 #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
00999 #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
01000 #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
01001
01002 #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
01003 #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
01004 #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
01005 #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
01006 #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
01007 #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
01008 #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
01009 #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
01010
01011
01012
01013 #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
01014 #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
01015 #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
01016 #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
01017
01018
01019
01020
01021 typedef struct _AT91S_TWI {
01022 AT91_REG TWI_CR;
01023 AT91_REG TWI_MMR;
01024 AT91_REG Reserved0[1];
01025 AT91_REG TWI_IADR;
01026 AT91_REG TWI_CWGR;
01027 AT91_REG Reserved1[3];
01028 AT91_REG TWI_SR;
01029 AT91_REG TWI_IER;
01030 AT91_REG TWI_IDR;
01031 AT91_REG TWI_IMR;
01032 AT91_REG TWI_RHR;
01033 AT91_REG TWI_THR;
01034 } AT91S_TWI, *AT91PS_TWI;
01035
01036
01037 #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
01038 #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
01039 #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
01040 #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
01041 #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
01042
01043 #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
01044 #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
01045 #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
01046 #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
01047 #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
01048 #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
01049 #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
01050
01051 #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
01052 #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
01053 #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
01054
01055 #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
01056 #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
01057 #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
01058 #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
01059 #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
01060 #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
01061
01062
01063
01064
01065
01066
01067
01068 typedef struct _AT91S_TC {
01069 AT91_REG TC_CCR;
01070 AT91_REG TC_CMR;
01071 AT91_REG Reserved0[2];
01072 AT91_REG TC_CV;
01073 AT91_REG TC_RA;
01074 AT91_REG TC_RB;
01075 AT91_REG TC_RC;
01076 AT91_REG TC_SR;
01077 AT91_REG TC_IER;
01078 AT91_REG TC_IDR;
01079 AT91_REG TC_IMR;
01080 } AT91S_TC, *AT91PS_TC;
01081
01082
01083 #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
01084 #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
01085 #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
01086
01087 #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
01088 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
01089 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
01090 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
01091 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
01092 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
01093 #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
01094 #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
01095 #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
01096 #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
01097 #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
01098 #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
01099 #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
01100 #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
01101 #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
01102 #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
01103 #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
01104 #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
01105 #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
01106 #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
01107 #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
01108 #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
01109 #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
01110 #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
01111 #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
01112 #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
01113 #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
01114 #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
01115 #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
01116 #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
01117 #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
01118 #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
01119 #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
01120 #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
01121 #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
01122 #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
01123 #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
01124 #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
01125 #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
01126 #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
01127 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
01128 #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
01129 #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
01130 #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
01131 #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
01132 #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
01133 #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
01134 #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
01135 #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
01136 #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
01137 #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
01138 #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
01139 #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
01140 #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
01141 #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
01142 #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
01143 #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
01144 #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
01145 #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
01146 #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
01147 #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
01148 #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
01149 #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
01150 #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
01151 #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
01152 #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
01153 #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
01154 #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
01155 #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
01156 #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
01157 #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
01158 #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
01159 #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
01160 #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
01161 #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
01162 #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
01163 #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
01164 #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
01165 #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
01166 #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
01167 #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
01168 #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
01169 #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
01170 #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
01171 #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
01172 #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
01173 #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
01174 #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
01175 #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
01176 #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
01177 #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
01178 #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
01179 #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
01180
01181 #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
01182 #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
01183 #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
01184 #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
01185 #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
01186 #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
01187 #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
01188 #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
01189 #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
01190 #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
01191 #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
01192
01193
01194
01195
01196
01197
01198
01199 typedef struct _AT91S_TCB {
01200 AT91S_TC TCB_TC0;
01201 AT91_REG Reserved0[4];
01202 AT91S_TC TCB_TC1;
01203 AT91_REG Reserved1[4];
01204 AT91S_TC TCB_TC2;
01205 AT91_REG Reserved2[4];
01206 AT91_REG TCB_BCR;
01207 AT91_REG TCB_BMR;
01208 } AT91S_TCB, *AT91PS_TCB;
01209
01210
01211 #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
01212
01213 #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
01214 #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
01215 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
01216 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
01217 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
01218 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
01219 #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
01220 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
01221 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
01222 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
01223 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
01224 #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
01225 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
01226 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
01227 #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
01228
01229
01230
01231
01232 typedef struct _AT91S_PWMC_CH {
01233 AT91_REG PWMC_CMR;
01234 AT91_REG PWMC_CDTYR;
01235 AT91_REG PWMC_CPRDR;
01236 AT91_REG PWMC_CCNTR;
01237 AT91_REG PWMC_CUPDR;
01238 AT91_REG PWMC_Reserved[3];
01239 } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
01240
01241
01242 #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
01243 #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
01244 #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
01245 #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
01246 #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
01247 #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
01248 #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
01249
01250 #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
01251
01252 #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
01253
01254 #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
01255
01256 #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
01257
01258
01259
01260
01261 typedef struct _AT91S_PWMC {
01262 AT91_REG PWMC_MR;
01263 AT91_REG PWMC_ENA;
01264 AT91_REG PWMC_DIS;
01265 AT91_REG PWMC_SR;
01266 AT91_REG PWMC_IER;
01267 AT91_REG PWMC_IDR;
01268 AT91_REG PWMC_IMR;
01269 AT91_REG PWMC_ISR;
01270 AT91_REG Reserved0[55];
01271 AT91_REG PWMC_VR;
01272 AT91_REG Reserved1[64];
01273 AT91S_PWMC_CH PWMC_CH[32];
01274 } AT91S_PWMC, *AT91PS_PWMC;
01275
01276
01277 #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
01278 #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
01279 #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
01280 #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
01281 #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
01282 #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
01283
01284 #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
01285 #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
01286 #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
01287 #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
01288 #define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4
01289 #define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5
01290 #define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6
01291 #define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7
01292
01293
01294
01295
01296
01297
01298
01299
01300
01301
01302 typedef struct _AT91S_UDP {
01303 AT91_REG UDP_NUM;
01304 AT91_REG UDP_GLBSTATE;
01305 AT91_REG UDP_FADDR;
01306 AT91_REG Reserved0[1];
01307 AT91_REG UDP_IER;
01308 AT91_REG UDP_IDR;
01309 AT91_REG UDP_IMR;
01310 AT91_REG UDP_ISR;
01311 AT91_REG UDP_ICR;
01312 AT91_REG Reserved1[1];
01313 AT91_REG UDP_RSTEP;
01314 AT91_REG Reserved2[1];
01315 AT91_REG UDP_CSR[8];
01316 AT91_REG UDP_FDR[8];
01317 AT91_REG Reserved3[1];
01318 AT91_REG UDP_TXVC;
01319 } AT91S_UDP, *AT91PS_UDP;
01320
01321
01322 #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
01323 #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
01324 #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
01325
01326 #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
01327 #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
01328 #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
01329 #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
01330 #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
01331
01332 #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
01333 #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
01334
01335 #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
01336 #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
01337 #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
01338 #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
01339 #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
01340 #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
01341 #define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
01342 #define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
01343 #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
01344 #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
01345 #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
01346 #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
01347 #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
01348
01349
01350
01351 #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
01352
01353
01354 #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
01355 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
01356 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
01357 #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
01358 #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
01359 #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
01360 #define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
01361 #define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
01362
01363 #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
01364 #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
01365 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
01366 #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
01367 #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
01368 #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
01369 #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
01370 #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
01371 #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
01372 #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
01373 #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
01374 #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
01375 #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
01376 #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
01377 #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
01378 #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
01379 #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
01380 #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
01381 #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
01382
01383 #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
01384 #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
01385
01386
01387
01388
01389
01390
01391 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
01392 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
01393 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
01394 #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
01395 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
01396 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
01397 #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
01398 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
01399 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
01400 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
01401 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
01402 #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
01403 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
01404 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
01405 #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
01406 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
01407 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
01408 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
01409
01410 #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
01411 #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
01412 #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
01413 #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
01414 #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
01415 #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
01416 #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
01417 #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
01418 #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
01419 #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
01420
01421 #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
01422 #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
01423 #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
01424 #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
01425 #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
01426 #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
01427 #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
01428 #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
01429 #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
01430 #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
01431 #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
01432 #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
01433
01434 #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
01435 #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
01436 #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
01437 #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
01438 #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
01439 #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
01440 #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
01441 #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
01442 #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
01443 #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
01444 #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
01445 #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
01446 #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
01447 #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
01448 #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
01449 #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
01450 #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
01451 #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
01452 #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
01453 #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
01454 #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
01455 #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
01456 #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
01457 #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
01458 #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
01459 #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
01460 #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
01461 #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
01462 #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
01463
01464 #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
01465 #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
01466 #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
01467
01468 #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
01469 #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
01470 #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
01471 #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
01472 #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
01473 #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
01474 #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
01475 #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
01476 #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
01477 #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
01478 #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
01479 #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
01480 #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
01481 #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
01482 #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
01483
01484 #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
01485 #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
01486 #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
01487
01488 #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
01489 #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
01490 #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
01491 #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
01492
01493 #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
01494 #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
01495 #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
01496 #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
01497
01498 #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
01499 #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
01500 #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
01501
01502 #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
01503
01504 #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
01505 #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
01506 #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
01507 #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
01508 #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
01509 #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
01510
01511 #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
01512 #define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
01513 #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
01514 #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
01515 #define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
01516 #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
01517 #define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
01518 #define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
01519 #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
01520 #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
01521
01522 #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
01523 #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
01524 #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
01525 #define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
01526 #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
01527 #define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
01528 #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
01529 #define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
01530 #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
01531
01532 #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
01533 #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
01534 #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
01535 #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
01536 #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
01537 #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
01538 #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
01539 #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
01540 #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
01541 #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
01542
01543 #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
01544 #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
01545 #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
01546 #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
01547 #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
01548 #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
01549 #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
01550 #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
01551 #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
01552 #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
01553 #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
01554 #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
01555 #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
01556 #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
01557 #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
01558 #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
01559 #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
01560 #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
01561
01562 #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
01563 #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
01564 #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
01565 #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
01566 #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
01567 #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
01568 #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
01569 #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
01570 #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
01571 #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
01572
01573 #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
01574 #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
01575 #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
01576 #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
01577 #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
01578 #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
01579 #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
01580 #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
01581 #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
01582 #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
01583 #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
01584 #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
01585 #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
01586 #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
01587
01588 #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
01589 #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
01590 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
01591 #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
01592 #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
01593 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
01594 #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
01595 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
01596 #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
01597 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
01598
01599 #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
01600 #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
01601 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
01602 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
01603 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
01604 #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
01605 #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
01606 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
01607 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
01608 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
01609 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
01610 #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
01611 #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
01612 #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
01613
01614 #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
01615 #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
01616 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
01617 #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
01618 #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
01619 #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
01620 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
01621 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
01622 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
01623 #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
01624
01625 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
01626 #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
01627 #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
01628 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
01629 #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
01630 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
01631 #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
01632 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
01633 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
01634 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
01635 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
01636 #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
01637 #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
01638 #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
01639
01640 #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
01641 #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
01642 #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
01643 #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
01644 #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
01645 #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
01646 #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
01647 #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
01648 #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
01649 #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
01650
01651 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
01652 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
01653 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
01654 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
01655 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
01656 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
01657 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
01658 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
01659 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
01660 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
01661
01662 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
01663 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
01664 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
01665 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
01666 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
01667 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
01668 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
01669 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
01670 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
01671 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
01672
01673 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
01674 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
01675 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
01676 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
01677 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
01678 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
01679 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
01680 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
01681 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
01682 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
01683
01684 #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
01685 #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
01686
01687 #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
01688 #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
01689 #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
01690 #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
01691 #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
01692 #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
01693
01694 #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
01695 #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
01696 #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
01697 #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
01698 #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
01699 #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
01700
01701 #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
01702 #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
01703 #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
01704 #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
01705 #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
01706 #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
01707
01708 #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
01709 #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
01710 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
01711 #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
01712 #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
01713 #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
01714
01715 #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
01716 #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
01717 #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
01718 #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
01719 #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
01720 #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
01721 #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
01722 #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
01723 #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
01724
01725 #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
01726 #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
01727 #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
01728 #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
01729 #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
01730 #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
01731 #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
01732 #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
01733 #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
01734 #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
01735 #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
01736 #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
01737
01738
01739
01740
01741 #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
01742 #define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
01743 #define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
01744 #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
01745 #define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
01746 #define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
01747 #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
01748 #define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
01749 #define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
01750 #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
01751 #define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
01752 #define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
01753 #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
01754 #define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
01755 #define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
01756 #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
01757 #define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
01758 #define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
01759 #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
01760 #define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
01761 #define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
01762 #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
01763 #define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
01764 #define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
01765 #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
01766 #define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
01767 #define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
01768 #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
01769 #define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
01770 #define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
01771 #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
01772 #define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
01773 #define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
01774 #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
01775 #define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
01776 #define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
01777 #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
01778 #define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
01779 #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
01780 #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
01781 #define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
01782 #define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
01783 #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
01784 #define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
01785 #define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
01786 #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
01787 #define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
01788 #define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
01789 #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
01790 #define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
01791 #define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
01792 #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
01793 #define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
01794 #define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
01795 #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
01796 #define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
01797 #define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
01798 #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
01799 #define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
01800 #define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
01801 #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
01802 #define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
01803 #define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
01804 #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
01805 #define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
01806 #define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
01807 #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
01808 #define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
01809 #define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
01810 #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
01811 #define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
01812 #define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
01813 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
01814 #define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
01815 #define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
01816 #define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
01817 #define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
01818 #define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
01819 #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
01820 #define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
01821 #define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
01822 #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
01823 #define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
01824 #define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
01825 #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
01826 #define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
01827 #define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
01828 #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
01829 #define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
01830 #define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
01831 #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
01832 #define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
01833 #define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
01834 #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
01835 #define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
01836 #define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
01837
01838
01839
01840
01841 #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
01842 #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
01843 #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
01844 #define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
01845 #define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
01846 #define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
01847 #define AT91C_ID_US0 ((unsigned int) 6) // USART 0
01848 #define AT91C_ID_US1 ((unsigned int) 7) // USART 1
01849 #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
01850 #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
01851 #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
01852 #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
01853 #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
01854 #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
01855 #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
01856 #define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
01857 #define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
01858 #define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
01859 #define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
01860 #define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
01861 #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
01862 #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
01863 #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
01864 #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
01865 #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
01866 #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
01867 #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
01868 #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
01869 #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
01870 #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
01871 #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
01872 #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
01873
01874
01875
01876
01877 #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
01878 #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
01879 #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
01880 #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
01881 #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
01882 #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
01883 #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
01884 #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
01885 #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
01886 #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
01887 #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
01888 #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
01889 #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
01890 #define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
01891 #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
01892 #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
01893 #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
01894 #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
01895 #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
01896 #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
01897 #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
01898 #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
01899 #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
01900 #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
01901 #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
01902 #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
01903 #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
01904 #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
01905 #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
01906 #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
01907 #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
01908 #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
01909 #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
01910 #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
01911
01912
01913
01914
01915 #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
01916 #define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
01917 #define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
01918 #define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
01919
01920 #endif
