00001 //* ---------------------------------------------------------------------------- 00002 //* ATMEL Microcontroller Software Support - ROUSSET - 00003 //* ---------------------------------------------------------------------------- 00004 //* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 00005 //* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00006 //* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00007 //* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 00008 //* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00009 //* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 00010 //* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 00011 //* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 00012 //* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00013 //* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00014 //* ---------------------------------------------------------------------------- 00015 //* File Name : lib_AT91SAM7S64.h 00016 //* Object : AT91SAM7S64 inlined functions 00017 //* Generated : AT91 SW Application Group 03/08/2005 (15:46:05) 00018 //* 00019 //* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// 00020 //* CVS Reference : /lib_pmc_SAM7S.h/1.1/Tue Feb 1 08:32:10 2005// 00021 //* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// 00022 //* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// 00023 //* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// 00024 //* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// 00025 //* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// 00026 //* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// 00027 //* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// 00028 //* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 08:46:12 2002// 00029 //* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// 00030 //* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// 00031 //* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// 00032 //* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// 00033 //* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// 00034 //* CVS Reference : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004// 00035 //* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// 00036 //* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// 00037 //* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// 00038 //* ---------------------------------------------------------------------------- 00039 00040 #ifndef lib_AT91SAM7S64_H 00041 #define lib_AT91SAM7S64_H 00042 00043 /* ***************************************************************************** 00044 SOFTWARE API FOR AIC 00045 ***************************************************************************** */ 00046 #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] 00047 00048 //*---------------------------------------------------------------------------- 00049 //* \fn AT91F_AIC_ConfigureIt 00050 //* \brief Interrupt Handler Initialization 00051 //*---------------------------------------------------------------------------- 00052 __inline unsigned int AT91F_AIC_ConfigureIt ( 00053 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00054 unsigned int irq_id, // \arg interrupt number to initialize 00055 unsigned int priority, // \arg priority to give to the interrupt 00056 unsigned int src_type, // \arg activation and sense of activation 00057 void (*newHandler) (void) ) // \arg address of the interrupt handler 00058 { 00059 unsigned int oldHandler; 00060 unsigned int mask ; 00061 00062 oldHandler = pAic->AIC_SVR[irq_id]; 00063 00064 mask = 0x1 << irq_id ; 00065 //* Disable the interrupt on the interrupt controller 00066 pAic->AIC_IDCR = mask ; 00067 //* Save the interrupt handler routine pointer and the interrupt priority 00068 pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; 00069 //* Store the Source Mode Register 00070 pAic->AIC_SMR[irq_id] = src_type | priority ; 00071 //* Clear the interrupt on the interrupt controller 00072 pAic->AIC_ICCR = mask ; 00073 00074 return oldHandler; 00075 } 00076 00077 //*---------------------------------------------------------------------------- 00078 //* \fn AT91F_AIC_EnableIt 00079 //* \brief Enable corresponding IT number 00080 //*---------------------------------------------------------------------------- 00081 __inline void AT91F_AIC_EnableIt ( 00082 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00083 unsigned int irq_id ) // \arg interrupt number to initialize 00084 { 00085 //* Enable the interrupt on the interrupt controller 00086 pAic->AIC_IECR = 0x1 << irq_id ; 00087 } 00088 00089 //*---------------------------------------------------------------------------- 00090 //* \fn AT91F_AIC_DisableIt 00091 //* \brief Disable corresponding IT number 00092 //*---------------------------------------------------------------------------- 00093 __inline void AT91F_AIC_DisableIt ( 00094 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00095 unsigned int irq_id ) // \arg interrupt number to initialize 00096 { 00097 unsigned int mask = 0x1 << irq_id; 00098 //* Disable the interrupt on the interrupt controller 00099 pAic->AIC_IDCR = mask ; 00100 //* Clear the interrupt on the Interrupt Controller ( if one is pending ) 00101 pAic->AIC_ICCR = mask ; 00102 } 00103 00104 //*---------------------------------------------------------------------------- 00105 //* \fn AT91F_AIC_ClearIt 00106 //* \brief Clear corresponding IT number 00107 //*---------------------------------------------------------------------------- 00108 __inline void AT91F_AIC_ClearIt ( 00109 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00110 unsigned int irq_id) // \arg interrupt number to initialize 00111 { 00112 //* Clear the interrupt on the Interrupt Controller ( if one is pending ) 00113 pAic->AIC_ICCR = (0x1 << irq_id); 00114 } 00115 00116 //*---------------------------------------------------------------------------- 00117 //* \fn AT91F_AIC_AcknowledgeIt 00118 //* \brief Acknowledge corresponding IT number 00119 //*---------------------------------------------------------------------------- 00120 __inline void AT91F_AIC_AcknowledgeIt ( 00121 AT91PS_AIC pAic) // \arg pointer to the AIC registers 00122 { 00123 pAic->AIC_EOICR = pAic->AIC_EOICR; 00124 } 00125 00126 //*---------------------------------------------------------------------------- 00127 //* \fn AT91F_AIC_SetExceptionVector 00128 //* \brief Configure vector handler 00129 //*---------------------------------------------------------------------------- 00130 __inline unsigned int AT91F_AIC_SetExceptionVector ( 00131 unsigned int *pVector, // \arg pointer to the AIC registers 00132 void (*Handler) () ) // \arg Interrupt Handler 00133 { 00134 unsigned int oldVector = *pVector; 00135 00136 if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) 00137 *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; 00138 else 00139 *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; 00140 00141 return oldVector; 00142 } 00143 00144 //*---------------------------------------------------------------------------- 00145 //* \fn AT91F_AIC_Trig 00146 //* \brief Trig an IT 00147 //*---------------------------------------------------------------------------- 00148 __inline void AT91F_AIC_Trig ( 00149 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00150 unsigned int irq_id) // \arg interrupt number 00151 { 00152 pAic->AIC_ISCR = (0x1 << irq_id) ; 00153 } 00154 00155 //*---------------------------------------------------------------------------- 00156 //* \fn AT91F_AIC_IsActive 00157 //* \brief Test if an IT is active 00158 //*---------------------------------------------------------------------------- 00159 __inline unsigned int AT91F_AIC_IsActive ( 00160 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00161 unsigned int irq_id) // \arg Interrupt Number 00162 { 00163 return (pAic->AIC_ISR & (0x1 << irq_id)); 00164 } 00165 00166 //*---------------------------------------------------------------------------- 00167 //* \fn AT91F_AIC_IsPending 00168 //* \brief Test if an IT is pending 00169 //*---------------------------------------------------------------------------- 00170 __inline unsigned int AT91F_AIC_IsPending ( 00171 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00172 unsigned int irq_id) // \arg Interrupt Number 00173 { 00174 return (pAic->AIC_IPR & (0x1 << irq_id)); 00175 } 00176 00177 //*---------------------------------------------------------------------------- 00178 //* \fn AT91F_AIC_Open 00179 //* \brief Set exception vectors and AIC registers to default values 00180 //*---------------------------------------------------------------------------- 00181 __inline void AT91F_AIC_Open( 00182 AT91PS_AIC pAic, // \arg pointer to the AIC registers 00183 void (*IrqHandler) (), // \arg Default IRQ vector exception 00184 void (*FiqHandler) (), // \arg Default FIQ vector exception 00185 void (*DefaultHandler) (), // \arg Default Handler set in ISR 00186 void (*SpuriousHandler) (), // \arg Default Spurious Handler 00187 unsigned int protectMode) // \arg Debug Control Register 00188 { 00189 int i; 00190 00191 // Disable all interrupts and set IVR to the default handler 00192 for (i = 0; i < 32; ++i) { 00193 AT91F_AIC_DisableIt(pAic, i); 00194 AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); 00195 } 00196 00197 // Set the IRQ exception vector 00198 AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); 00199 // Set the Fast Interrupt exception vector 00200 AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); 00201 00202 pAic->AIC_SPU = (unsigned int) SpuriousHandler; 00203 pAic->AIC_DCR = protectMode; 00204 } 00205 /* ***************************************************************************** 00206 SOFTWARE API FOR PDC 00207 ***************************************************************************** */ 00208 //*---------------------------------------------------------------------------- 00209 //* \fn AT91F_PDC_SetNextRx 00210 //* \brief Set the next receive transfer descriptor 00211 //*---------------------------------------------------------------------------- 00212 __inline void AT91F_PDC_SetNextRx ( 00213 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 00214 char *address, // \arg address to the next bloc to be received 00215 unsigned int bytes) // \arg number of bytes to be received 00216 { 00217 pPDC->PDC_RNPR = (unsigned int) address; 00218 pPDC->PDC_RNCR = bytes; 00219 } 00220 00221 //*---------------------------------------------------------------------------- 00222 //* \fn AT91F_PDC_SetNextTx 00223 //* \brief Set the next transmit transfer descriptor 00224 //*---------------------------------------------------------------------------- 00225 __inline void AT91F_PDC_SetNextTx ( 00226 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 00227 char *address, // \arg address to the next bloc to be transmitted 00228 unsigned int bytes) // \arg number of bytes to be transmitted 00229 { 00230 pPDC->PDC_TNPR = (unsigned int) address; 00231 pPDC->PDC_TNCR = bytes; 00232 } 00233 00234 //*---------------------------------------------------------------------------- 00235 //* \fn AT91F_PDC_SetRx 00236 //* \brief Set the receive transfer descriptor 00237 //*---------------------------------------------------------------------------- 00238 __inline void AT91F_PDC_SetRx ( 00239 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 00240 char *address, // \arg address to the next bloc to be received 00241 unsigned int bytes) // \arg number of bytes to be received 00242 { 00243 pPDC->PDC_RPR = (unsigned int) address; 00244 pPDC->PDC_RCR = bytes; 00245 } 00246 00247 //*---------------------------------------------------------------------------- 00248 //* \fn AT91F_PDC_SetTx 00249 //* \brief Set the transmit transfer descriptor 00250 //*---------------------------------------------------------------------------- 00251 __inline void AT91F_PDC_SetTx ( 00252 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 00253 char *address, // \arg address to the next bloc to be transmitted 00254 unsigned int bytes) // \arg number of bytes to be transmitted 00255 { 00256 pPDC->PDC_TPR = (unsigned int) address; 00257 pPDC->PDC_TCR = bytes; 00258 } 00259 00260 //*---------------------------------------------------------------------------- 00261 //* \fn AT91F_PDC_EnableTx 00262 //* \brief Enable transmit 00263 //*---------------------------------------------------------------------------- 00264 __inline void AT91F_PDC_EnableTx ( 00265 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00266 { 00267 pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 00268 } 00269 00270 //*---------------------------------------------------------------------------- 00271 //* \fn AT91F_PDC_EnableRx 00272 //* \brief Enable receive 00273 //*---------------------------------------------------------------------------- 00274 __inline void AT91F_PDC_EnableRx ( 00275 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00276 { 00277 pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 00278 } 00279 00280 //*---------------------------------------------------------------------------- 00281 //* \fn AT91F_PDC_DisableTx 00282 //* \brief Disable transmit 00283 //*---------------------------------------------------------------------------- 00284 __inline void AT91F_PDC_DisableTx ( 00285 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00286 { 00287 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 00288 } 00289 00290 //*---------------------------------------------------------------------------- 00291 //* \fn AT91F_PDC_DisableRx 00292 //* \brief Disable receive 00293 //*---------------------------------------------------------------------------- 00294 __inline void AT91F_PDC_DisableRx ( 00295 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00296 { 00297 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 00298 } 00299 00300 //*---------------------------------------------------------------------------- 00301 //* \fn AT91F_PDC_IsTxEmpty 00302 //* \brief Test if the current transfer descriptor has been sent 00303 //*---------------------------------------------------------------------------- 00304 __inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete 00305 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00306 { 00307 return !(pPDC->PDC_TCR); 00308 } 00309 00310 //*---------------------------------------------------------------------------- 00311 //* \fn AT91F_PDC_IsNextTxEmpty 00312 //* \brief Test if the next transfer descriptor has been moved to the current td 00313 //*---------------------------------------------------------------------------- 00314 __inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete 00315 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00316 { 00317 return !(pPDC->PDC_TNCR); 00318 } 00319 00320 //*---------------------------------------------------------------------------- 00321 //* \fn AT91F_PDC_IsRxEmpty 00322 //* \brief Test if the current transfer descriptor has been filled 00323 //*---------------------------------------------------------------------------- 00324 __inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete 00325 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00326 { 00327 return !(pPDC->PDC_RCR); 00328 } 00329 00330 //*---------------------------------------------------------------------------- 00331 //* \fn AT91F_PDC_IsNextRxEmpty 00332 //* \brief Test if the next transfer descriptor has been moved to the current td 00333 //*---------------------------------------------------------------------------- 00334 __inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete 00335 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 00336 { 00337 return !(pPDC->PDC_RNCR); 00338 } 00339 00340 //*---------------------------------------------------------------------------- 00341 //* \fn AT91F_PDC_Open 00342 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX 00343 //*---------------------------------------------------------------------------- 00344 __inline void AT91F_PDC_Open ( 00345 AT91PS_PDC pPDC) // \arg pointer to a PDC controller 00346 { 00347 //* Disable the RX and TX PDC transfer requests 00348 AT91F_PDC_DisableRx(pPDC); 00349 AT91F_PDC_DisableTx(pPDC); 00350 00351 //* Reset all Counter register Next buffer first 00352 AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); 00353 AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); 00354 AT91F_PDC_SetTx(pPDC, (char *) 0, 0); 00355 AT91F_PDC_SetRx(pPDC, (char *) 0, 0); 00356 00357 //* Enable the RX and TX PDC transfer requests 00358 AT91F_PDC_EnableRx(pPDC); 00359 AT91F_PDC_EnableTx(pPDC); 00360 } 00361 00362 //*---------------------------------------------------------------------------- 00363 //* \fn AT91F_PDC_Close 00364 //* \brief Close PDC: disable TX and RX reset transfer descriptors 00365 //*---------------------------------------------------------------------------- 00366 __inline void AT91F_PDC_Close ( 00367 AT91PS_PDC pPDC) // \arg pointer to a PDC controller 00368 { 00369 //* Disable the RX and TX PDC transfer requests 00370 AT91F_PDC_DisableRx(pPDC); 00371 AT91F_PDC_DisableTx(pPDC); 00372 00373 //* Reset all Counter register Next buffer first 00374 AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); 00375 AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); 00376 AT91F_PDC_SetTx(pPDC, (char *) 0, 0); 00377 AT91F_PDC_SetRx(pPDC, (char *) 0, 0); 00378 00379 } 00380 00381 //*---------------------------------------------------------------------------- 00382 //* \fn AT91F_PDC_SendFrame 00383 //* \brief Close PDC: disable TX and RX reset transfer descriptors 00384 //*---------------------------------------------------------------------------- 00385 __inline unsigned int AT91F_PDC_SendFrame( 00386 AT91PS_PDC pPDC, 00387 char *pBuffer, 00388 unsigned int szBuffer, 00389 char *pNextBuffer, 00390 unsigned int szNextBuffer ) 00391 { 00392 if (AT91F_PDC_IsTxEmpty(pPDC)) { 00393 //* Buffer and next buffer can be initialized 00394 AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); 00395 AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); 00396 return 2; 00397 } 00398 else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { 00399 //* Only one buffer can be initialized 00400 AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); 00401 return 1; 00402 } 00403 else { 00404 //* All buffer are in use... 00405 return 0; 00406 } 00407 } 00408 00409 //*---------------------------------------------------------------------------- 00410 //* \fn AT91F_PDC_ReceiveFrame 00411 //* \brief Close PDC: disable TX and RX reset transfer descriptors 00412 //*---------------------------------------------------------------------------- 00413 __inline unsigned int AT91F_PDC_ReceiveFrame ( 00414 AT91PS_PDC pPDC, 00415 char *pBuffer, 00416 unsigned int szBuffer, 00417 char *pNextBuffer, 00418 unsigned int szNextBuffer ) 00419 { 00420 if (AT91F_PDC_IsRxEmpty(pPDC)) { 00421 //* Buffer and next buffer can be initialized 00422 AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); 00423 AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); 00424 return 2; 00425 } 00426 else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { 00427 //* Only one buffer can be initialized 00428 AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); 00429 return 1; 00430 } 00431 else { 00432 //* All buffer are in use... 00433 return 0; 00434 } 00435 } 00436 /* ***************************************************************************** 00437 SOFTWARE API FOR DBGU 00438 ***************************************************************************** */ 00439 //*---------------------------------------------------------------------------- 00440 //* \fn AT91F_DBGU_InterruptEnable 00441 //* \brief Enable DBGU Interrupt 00442 //*---------------------------------------------------------------------------- 00443 __inline void AT91F_DBGU_InterruptEnable( 00444 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 00445 unsigned int flag) // \arg dbgu interrupt to be enabled 00446 { 00447 pDbgu->DBGU_IER = flag; 00448 } 00449 00450 //*---------------------------------------------------------------------------- 00451 //* \fn AT91F_DBGU_InterruptDisable 00452 //* \brief Disable DBGU Interrupt 00453 //*---------------------------------------------------------------------------- 00454 __inline void AT91F_DBGU_InterruptDisable( 00455 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 00456 unsigned int flag) // \arg dbgu interrupt to be disabled 00457 { 00458 pDbgu->DBGU_IDR = flag; 00459 } 00460 00461 //*---------------------------------------------------------------------------- 00462 //* \fn AT91F_DBGU_GetInterruptMaskStatus 00463 //* \brief Return DBGU Interrupt Mask Status 00464 //*---------------------------------------------------------------------------- 00465 __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status 00466 AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller 00467 { 00468 return pDbgu->DBGU_IMR; 00469 } 00470 00471 //*---------------------------------------------------------------------------- 00472 //* \fn AT91F_DBGU_IsInterruptMasked 00473 //* \brief Test if DBGU Interrupt is Masked 00474 //*---------------------------------------------------------------------------- 00475 __inline int AT91F_DBGU_IsInterruptMasked( 00476 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 00477 unsigned int flag) // \arg flag to be tested 00478 { 00479 return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); 00480 } 00481 00482 /* ***************************************************************************** 00483 SOFTWARE API FOR PIO 00484 ***************************************************************************** */ 00485 //*---------------------------------------------------------------------------- 00486 //* \fn AT91F_PIO_CfgPeriph 00487 //* \brief Enable pins to be drived by peripheral 00488 //*---------------------------------------------------------------------------- 00489 __inline void AT91F_PIO_CfgPeriph( 00490 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00491 unsigned int periphAEnable, // \arg PERIPH A to enable 00492 unsigned int periphBEnable) // \arg PERIPH B to enable 00493 00494 { 00495 pPio->PIO_ASR = periphAEnable; 00496 pPio->PIO_BSR = periphBEnable; 00497 pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode 00498 } 00499 00500 //*---------------------------------------------------------------------------- 00501 //* \fn AT91F_PIO_CfgOutput 00502 //* \brief Enable PIO in output mode 00503 //*---------------------------------------------------------------------------- 00504 __inline void AT91F_PIO_CfgOutput( 00505 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00506 unsigned int pioEnable) // \arg PIO to be enabled 00507 { 00508 pPio->PIO_PER = pioEnable; // Set in PIO mode 00509 pPio->PIO_OER = pioEnable; // Configure in Output 00510 } 00511 00512 //*---------------------------------------------------------------------------- 00513 //* \fn AT91F_PIO_CfgInput 00514 //* \brief Enable PIO in input mode 00515 //*---------------------------------------------------------------------------- 00516 __inline void AT91F_PIO_CfgInput( 00517 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00518 unsigned int inputEnable) // \arg PIO to be enabled 00519 { 00520 // Disable output 00521 pPio->PIO_ODR = inputEnable; 00522 pPio->PIO_PER = inputEnable; 00523 } 00524 00525 //*---------------------------------------------------------------------------- 00526 //* \fn AT91F_PIO_CfgOpendrain 00527 //* \brief Configure PIO in open drain 00528 //*---------------------------------------------------------------------------- 00529 __inline void AT91F_PIO_CfgOpendrain( 00530 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00531 unsigned int multiDrvEnable) // \arg pio to be configured in open drain 00532 { 00533 // Configure the multi-drive option 00534 pPio->PIO_MDDR = ~multiDrvEnable; 00535 pPio->PIO_MDER = multiDrvEnable; 00536 } 00537 00538 //*---------------------------------------------------------------------------- 00539 //* \fn AT91F_PIO_CfgPullup 00540 //* \brief Enable pullup on PIO 00541 //*---------------------------------------------------------------------------- 00542 __inline void AT91F_PIO_CfgPullup( 00543 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00544 unsigned int pullupEnable) // \arg enable pullup on PIO 00545 { 00546 // Connect or not Pullup 00547 pPio->PIO_PPUDR = ~pullupEnable; 00548 pPio->PIO_PPUER = pullupEnable; 00549 } 00550 00551 //*---------------------------------------------------------------------------- 00552 //* \fn AT91F_PIO_CfgDirectDrive 00553 //* \brief Enable direct drive on PIO 00554 //*---------------------------------------------------------------------------- 00555 __inline void AT91F_PIO_CfgDirectDrive( 00556 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00557 unsigned int directDrive) // \arg PIO to be configured with direct drive 00558 00559 { 00560 // Configure the Direct Drive 00561 pPio->PIO_OWDR = ~directDrive; 00562 pPio->PIO_OWER = directDrive; 00563 } 00564 00565 //*---------------------------------------------------------------------------- 00566 //* \fn AT91F_PIO_CfgInputFilter 00567 //* \brief Enable input filter on input PIO 00568 //*---------------------------------------------------------------------------- 00569 __inline void AT91F_PIO_CfgInputFilter( 00570 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00571 unsigned int inputFilter) // \arg PIO to be configured with input filter 00572 00573 { 00574 // Configure the Direct Drive 00575 pPio->PIO_IFDR = ~inputFilter; 00576 pPio->PIO_IFER = inputFilter; 00577 } 00578 00579 //*---------------------------------------------------------------------------- 00580 //* \fn AT91F_PIO_GetInput 00581 //* \brief Return PIO input value 00582 //*---------------------------------------------------------------------------- 00583 __inline unsigned int AT91F_PIO_GetInput( // \return PIO input 00584 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00585 { 00586 return pPio->PIO_PDSR; 00587 } 00588 00589 //*---------------------------------------------------------------------------- 00590 //* \fn AT91F_PIO_IsInputSet 00591 //* \brief Test if PIO is input flag is active 00592 //*---------------------------------------------------------------------------- 00593 __inline int AT91F_PIO_IsInputSet( 00594 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00595 unsigned int flag) // \arg flag to be tested 00596 { 00597 return (AT91F_PIO_GetInput(pPio) & flag); 00598 } 00599 00600 00601 //*---------------------------------------------------------------------------- 00602 //* \fn AT91F_PIO_SetOutput 00603 //* \brief Set to 1 output PIO 00604 //*---------------------------------------------------------------------------- 00605 __inline void AT91F_PIO_SetOutput( 00606 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00607 unsigned int flag) // \arg output to be set 00608 { 00609 pPio->PIO_SODR = flag; 00610 } 00611 00612 //*---------------------------------------------------------------------------- 00613 //* \fn AT91F_PIO_ClearOutput 00614 //* \brief Set to 0 output PIO 00615 //*---------------------------------------------------------------------------- 00616 __inline void AT91F_PIO_ClearOutput( 00617 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00618 unsigned int flag) // \arg output to be cleared 00619 { 00620 pPio->PIO_CODR = flag; 00621 } 00622 00623 //*---------------------------------------------------------------------------- 00624 //* \fn AT91F_PIO_ForceOutput 00625 //* \brief Force output when Direct drive option is enabled 00626 //*---------------------------------------------------------------------------- 00627 __inline void AT91F_PIO_ForceOutput( 00628 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00629 unsigned int flag) // \arg output to be forced 00630 { 00631 pPio->PIO_ODSR = flag; 00632 } 00633 00634 //*---------------------------------------------------------------------------- 00635 //* \fn AT91F_PIO_Enable 00636 //* \brief Enable PIO 00637 //*---------------------------------------------------------------------------- 00638 __inline void AT91F_PIO_Enable( 00639 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00640 unsigned int flag) // \arg pio to be enabled 00641 { 00642 pPio->PIO_PER = flag; 00643 } 00644 00645 //*---------------------------------------------------------------------------- 00646 //* \fn AT91F_PIO_Disable 00647 //* \brief Disable PIO 00648 //*---------------------------------------------------------------------------- 00649 __inline void AT91F_PIO_Disable( 00650 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00651 unsigned int flag) // \arg pio to be disabled 00652 { 00653 pPio->PIO_PDR = flag; 00654 } 00655 00656 //*---------------------------------------------------------------------------- 00657 //* \fn AT91F_PIO_GetStatus 00658 //* \brief Return PIO Status 00659 //*---------------------------------------------------------------------------- 00660 __inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status 00661 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00662 { 00663 return pPio->PIO_PSR; 00664 } 00665 00666 //*---------------------------------------------------------------------------- 00667 //* \fn AT91F_PIO_IsSet 00668 //* \brief Test if PIO is Set 00669 //*---------------------------------------------------------------------------- 00670 __inline int AT91F_PIO_IsSet( 00671 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00672 unsigned int flag) // \arg flag to be tested 00673 { 00674 return (AT91F_PIO_GetStatus(pPio) & flag); 00675 } 00676 00677 //*---------------------------------------------------------------------------- 00678 //* \fn AT91F_PIO_OutputEnable 00679 //* \brief Output Enable PIO 00680 //*---------------------------------------------------------------------------- 00681 __inline void AT91F_PIO_OutputEnable( 00682 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00683 unsigned int flag) // \arg pio output to be enabled 00684 { 00685 pPio->PIO_OER = flag; 00686 } 00687 00688 //*---------------------------------------------------------------------------- 00689 //* \fn AT91F_PIO_OutputDisable 00690 //* \brief Output Enable PIO 00691 //*---------------------------------------------------------------------------- 00692 __inline void AT91F_PIO_OutputDisable( 00693 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00694 unsigned int flag) // \arg pio output to be disabled 00695 { 00696 pPio->PIO_ODR = flag; 00697 } 00698 00699 //*---------------------------------------------------------------------------- 00700 //* \fn AT91F_PIO_GetOutputStatus 00701 //* \brief Return PIO Output Status 00702 //*---------------------------------------------------------------------------- 00703 __inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status 00704 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00705 { 00706 return pPio->PIO_OSR; 00707 } 00708 00709 //*---------------------------------------------------------------------------- 00710 //* \fn AT91F_PIO_IsOuputSet 00711 //* \brief Test if PIO Output is Set 00712 //*---------------------------------------------------------------------------- 00713 __inline int AT91F_PIO_IsOutputSet( 00714 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00715 unsigned int flag) // \arg flag to be tested 00716 { 00717 return (AT91F_PIO_GetOutputStatus(pPio) & flag); 00718 } 00719 00720 //*---------------------------------------------------------------------------- 00721 //* \fn AT91F_PIO_InputFilterEnable 00722 //* \brief Input Filter Enable PIO 00723 //*---------------------------------------------------------------------------- 00724 __inline void AT91F_PIO_InputFilterEnable( 00725 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00726 unsigned int flag) // \arg pio input filter to be enabled 00727 { 00728 pPio->PIO_IFER = flag; 00729 } 00730 00731 //*---------------------------------------------------------------------------- 00732 //* \fn AT91F_PIO_InputFilterDisable 00733 //* \brief Input Filter Disable PIO 00734 //*---------------------------------------------------------------------------- 00735 __inline void AT91F_PIO_InputFilterDisable( 00736 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00737 unsigned int flag) // \arg pio input filter to be disabled 00738 { 00739 pPio->PIO_IFDR = flag; 00740 } 00741 00742 //*---------------------------------------------------------------------------- 00743 //* \fn AT91F_PIO_GetInputFilterStatus 00744 //* \brief Return PIO Input Filter Status 00745 //*---------------------------------------------------------------------------- 00746 __inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status 00747 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00748 { 00749 return pPio->PIO_IFSR; 00750 } 00751 00752 //*---------------------------------------------------------------------------- 00753 //* \fn AT91F_PIO_IsInputFilterSet 00754 //* \brief Test if PIO Input filter is Set 00755 //*---------------------------------------------------------------------------- 00756 __inline int AT91F_PIO_IsInputFilterSet( 00757 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00758 unsigned int flag) // \arg flag to be tested 00759 { 00760 return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); 00761 } 00762 00763 //*---------------------------------------------------------------------------- 00764 //* \fn AT91F_PIO_GetOutputDataStatus 00765 //* \brief Return PIO Output Data Status 00766 //*---------------------------------------------------------------------------- 00767 __inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 00768 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00769 { 00770 return pPio->PIO_ODSR; 00771 } 00772 00773 //*---------------------------------------------------------------------------- 00774 //* \fn AT91F_PIO_InterruptEnable 00775 //* \brief Enable PIO Interrupt 00776 //*---------------------------------------------------------------------------- 00777 __inline void AT91F_PIO_InterruptEnable( 00778 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00779 unsigned int flag) // \arg pio interrupt to be enabled 00780 { 00781 pPio->PIO_IER = flag; 00782 } 00783 00784 //*---------------------------------------------------------------------------- 00785 //* \fn AT91F_PIO_InterruptDisable 00786 //* \brief Disable PIO Interrupt 00787 //*---------------------------------------------------------------------------- 00788 __inline void AT91F_PIO_InterruptDisable( 00789 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00790 unsigned int flag) // \arg pio interrupt to be disabled 00791 { 00792 pPio->PIO_IDR = flag; 00793 } 00794 00795 //*---------------------------------------------------------------------------- 00796 //* \fn AT91F_PIO_GetInterruptMaskStatus 00797 //* \brief Return PIO Interrupt Mask Status 00798 //*---------------------------------------------------------------------------- 00799 __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status 00800 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00801 { 00802 return pPio->PIO_IMR; 00803 } 00804 00805 //*---------------------------------------------------------------------------- 00806 //* \fn AT91F_PIO_GetInterruptStatus 00807 //* \brief Return PIO Interrupt Status 00808 //*---------------------------------------------------------------------------- 00809 __inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status 00810 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00811 { 00812 return pPio->PIO_ISR; 00813 } 00814 00815 //*---------------------------------------------------------------------------- 00816 //* \fn AT91F_PIO_IsInterruptMasked 00817 //* \brief Test if PIO Interrupt is Masked 00818 //*---------------------------------------------------------------------------- 00819 __inline int AT91F_PIO_IsInterruptMasked( 00820 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00821 unsigned int flag) // \arg flag to be tested 00822 { 00823 return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); 00824 } 00825 00826 //*---------------------------------------------------------------------------- 00827 //* \fn AT91F_PIO_IsInterruptSet 00828 //* \brief Test if PIO Interrupt is Set 00829 //*---------------------------------------------------------------------------- 00830 __inline int AT91F_PIO_IsInterruptSet( 00831 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00832 unsigned int flag) // \arg flag to be tested 00833 { 00834 return (AT91F_PIO_GetInterruptStatus(pPio) & flag); 00835 } 00836 00837 //*---------------------------------------------------------------------------- 00838 //* \fn AT91F_PIO_MultiDriverEnable 00839 //* \brief Multi Driver Enable PIO 00840 //*---------------------------------------------------------------------------- 00841 __inline void AT91F_PIO_MultiDriverEnable( 00842 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00843 unsigned int flag) // \arg pio to be enabled 00844 { 00845 pPio->PIO_MDER = flag; 00846 } 00847 00848 //*---------------------------------------------------------------------------- 00849 //* \fn AT91F_PIO_MultiDriverDisable 00850 //* \brief Multi Driver Disable PIO 00851 //*---------------------------------------------------------------------------- 00852 __inline void AT91F_PIO_MultiDriverDisable( 00853 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00854 unsigned int flag) // \arg pio to be disabled 00855 { 00856 pPio->PIO_MDDR = flag; 00857 } 00858 00859 //*---------------------------------------------------------------------------- 00860 //* \fn AT91F_PIO_GetMultiDriverStatus 00861 //* \brief Return PIO Multi Driver Status 00862 //*---------------------------------------------------------------------------- 00863 __inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status 00864 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00865 { 00866 return pPio->PIO_MDSR; 00867 } 00868 00869 //*---------------------------------------------------------------------------- 00870 //* \fn AT91F_PIO_IsMultiDriverSet 00871 //* \brief Test if PIO MultiDriver is Set 00872 //*---------------------------------------------------------------------------- 00873 __inline int AT91F_PIO_IsMultiDriverSet( 00874 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00875 unsigned int flag) // \arg flag to be tested 00876 { 00877 return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); 00878 } 00879 00880 //*---------------------------------------------------------------------------- 00881 //* \fn AT91F_PIO_A_RegisterSelection 00882 //* \brief PIO A Register Selection 00883 //*---------------------------------------------------------------------------- 00884 __inline void AT91F_PIO_A_RegisterSelection( 00885 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00886 unsigned int flag) // \arg pio A register selection 00887 { 00888 pPio->PIO_ASR = flag; 00889 } 00890 00891 //*---------------------------------------------------------------------------- 00892 //* \fn AT91F_PIO_B_RegisterSelection 00893 //* \brief PIO B Register Selection 00894 //*---------------------------------------------------------------------------- 00895 __inline void AT91F_PIO_B_RegisterSelection( 00896 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00897 unsigned int flag) // \arg pio B register selection 00898 { 00899 pPio->PIO_BSR = flag; 00900 } 00901 00902 //*---------------------------------------------------------------------------- 00903 //* \fn AT91F_PIO_Get_AB_RegisterStatus 00904 //* \brief Return PIO Interrupt Status 00905 //*---------------------------------------------------------------------------- 00906 __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status 00907 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00908 { 00909 return pPio->PIO_ABSR; 00910 } 00911 00912 //*---------------------------------------------------------------------------- 00913 //* \fn AT91F_PIO_IsAB_RegisterSet 00914 //* \brief Test if PIO AB Register is Set 00915 //*---------------------------------------------------------------------------- 00916 __inline int AT91F_PIO_IsAB_RegisterSet( 00917 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00918 unsigned int flag) // \arg flag to be tested 00919 { 00920 return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); 00921 } 00922 00923 //*---------------------------------------------------------------------------- 00924 //* \fn AT91F_PIO_OutputWriteEnable 00925 //* \brief Output Write Enable PIO 00926 //*---------------------------------------------------------------------------- 00927 __inline void AT91F_PIO_OutputWriteEnable( 00928 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00929 unsigned int flag) // \arg pio output write to be enabled 00930 { 00931 pPio->PIO_OWER = flag; 00932 } 00933 00934 //*---------------------------------------------------------------------------- 00935 //* \fn AT91F_PIO_OutputWriteDisable 00936 //* \brief Output Write Disable PIO 00937 //*---------------------------------------------------------------------------- 00938 __inline void AT91F_PIO_OutputWriteDisable( 00939 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00940 unsigned int flag) // \arg pio output write to be disabled 00941 { 00942 pPio->PIO_OWDR = flag; 00943 } 00944 00945 //*---------------------------------------------------------------------------- 00946 //* \fn AT91F_PIO_GetOutputWriteStatus 00947 //* \brief Return PIO Output Write Status 00948 //*---------------------------------------------------------------------------- 00949 __inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status 00950 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00951 { 00952 return pPio->PIO_OWSR; 00953 } 00954 00955 //*---------------------------------------------------------------------------- 00956 //* \fn AT91F_PIO_IsOutputWriteSet 00957 //* \brief Test if PIO OutputWrite is Set 00958 //*---------------------------------------------------------------------------- 00959 __inline int AT91F_PIO_IsOutputWriteSet( 00960 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00961 unsigned int flag) // \arg flag to be tested 00962 { 00963 return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); 00964 } 00965 00966 //*---------------------------------------------------------------------------- 00967 //* \fn AT91F_PIO_GetCfgPullup 00968 //* \brief Return PIO Configuration Pullup 00969 //*---------------------------------------------------------------------------- 00970 __inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 00971 AT91PS_PIO pPio) // \arg pointer to a PIO controller 00972 { 00973 return pPio->PIO_PPUSR; 00974 } 00975 00976 //*---------------------------------------------------------------------------- 00977 //* \fn AT91F_PIO_IsOutputDataStatusSet 00978 //* \brief Test if PIO Output Data Status is Set 00979 //*---------------------------------------------------------------------------- 00980 __inline int AT91F_PIO_IsOutputDataStatusSet( 00981 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00982 unsigned int flag) // \arg flag to be tested 00983 { 00984 return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); 00985 } 00986 00987 //*---------------------------------------------------------------------------- 00988 //* \fn AT91F_PIO_IsCfgPullupStatusSet 00989 //* \brief Test if PIO Configuration Pullup Status is Set 00990 //*---------------------------------------------------------------------------- 00991 __inline int AT91F_PIO_IsCfgPullupStatusSet( 00992 AT91PS_PIO pPio, // \arg pointer to a PIO controller 00993 unsigned int flag) // \arg flag to be tested 00994 { 00995 return (~AT91F_PIO_GetCfgPullup(pPio) & flag); 00996 } 00997 00998 /* ***************************************************************************** 00999 SOFTWARE API FOR PMC 01000 ***************************************************************************** */ 01001 //*---------------------------------------------------------------------------- 01002 //* \fn AT91F_PMC_CfgSysClkEnableReg 01003 //* \brief Configure the System Clock Enable Register of the PMC controller 01004 //*---------------------------------------------------------------------------- 01005 __inline void AT91F_PMC_CfgSysClkEnableReg ( 01006 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01007 unsigned int mode) 01008 { 01009 //* Write to the SCER register 01010 pPMC->PMC_SCER = mode; 01011 } 01012 01013 //*---------------------------------------------------------------------------- 01014 //* \fn AT91F_PMC_CfgSysClkDisableReg 01015 //* \brief Configure the System Clock Disable Register of the PMC controller 01016 //*---------------------------------------------------------------------------- 01017 __inline void AT91F_PMC_CfgSysClkDisableReg ( 01018 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01019 unsigned int mode) 01020 { 01021 //* Write to the SCDR register 01022 pPMC->PMC_SCDR = mode; 01023 } 01024 01025 //*---------------------------------------------------------------------------- 01026 //* \fn AT91F_PMC_GetSysClkStatusReg 01027 //* \brief Return the System Clock Status Register of the PMC controller 01028 //*---------------------------------------------------------------------------- 01029 __inline unsigned int AT91F_PMC_GetSysClkStatusReg ( 01030 AT91PS_PMC pPMC // pointer to a CAN controller 01031 ) 01032 { 01033 return pPMC->PMC_SCSR; 01034 } 01035 01036 //*---------------------------------------------------------------------------- 01037 //* \fn AT91F_PMC_EnablePeriphClock 01038 //* \brief Enable peripheral clock 01039 //*---------------------------------------------------------------------------- 01040 __inline void AT91F_PMC_EnablePeriphClock ( 01041 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01042 unsigned int periphIds) // \arg IDs of peripherals to enable 01043 { 01044 pPMC->PMC_PCER = periphIds; 01045 } 01046 01047 //*---------------------------------------------------------------------------- 01048 //* \fn AT91F_PMC_DisablePeriphClock 01049 //* \brief Disable peripheral clock 01050 //*---------------------------------------------------------------------------- 01051 __inline void AT91F_PMC_DisablePeriphClock ( 01052 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01053 unsigned int periphIds) // \arg IDs of peripherals to enable 01054 { 01055 pPMC->PMC_PCDR = periphIds; 01056 } 01057 01058 //*---------------------------------------------------------------------------- 01059 //* \fn AT91F_PMC_GetPeriphClock 01060 //* \brief Get peripheral clock status 01061 //*---------------------------------------------------------------------------- 01062 __inline unsigned int AT91F_PMC_GetPeriphClock ( 01063 AT91PS_PMC pPMC) // \arg pointer to PMC controller 01064 { 01065 return pPMC->PMC_PCSR; 01066 } 01067 01068 //*---------------------------------------------------------------------------- 01069 //* \fn AT91F_CKGR_CfgMainOscillatorReg 01070 //* \brief Cfg the main oscillator 01071 //*---------------------------------------------------------------------------- 01072 __inline void AT91F_CKGR_CfgMainOscillatorReg ( 01073 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 01074 unsigned int mode) 01075 { 01076 pCKGR->CKGR_MOR = mode; 01077 } 01078 01079 //*---------------------------------------------------------------------------- 01080 //* \fn AT91F_CKGR_GetMainOscillatorReg 01081 //* \brief Cfg the main oscillator 01082 //*---------------------------------------------------------------------------- 01083 __inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( 01084 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 01085 { 01086 return pCKGR->CKGR_MOR; 01087 } 01088 01089 //*---------------------------------------------------------------------------- 01090 //* \fn AT91F_CKGR_EnableMainOscillator 01091 //* \brief Enable the main oscillator 01092 //*---------------------------------------------------------------------------- 01093 __inline void AT91F_CKGR_EnableMainOscillator( 01094 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 01095 { 01096 pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; 01097 } 01098 01099 //*---------------------------------------------------------------------------- 01100 //* \fn AT91F_CKGR_DisableMainOscillator 01101 //* \brief Disable the main oscillator 01102 //*---------------------------------------------------------------------------- 01103 __inline void AT91F_CKGR_DisableMainOscillator ( 01104 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 01105 { 01106 pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; 01107 } 01108 01109 //*---------------------------------------------------------------------------- 01110 //* \fn AT91F_CKGR_CfgMainOscStartUpTime 01111 //* \brief Cfg MOR Register according to the main osc startup time 01112 //*---------------------------------------------------------------------------- 01113 __inline void AT91F_CKGR_CfgMainOscStartUpTime ( 01114 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 01115 unsigned int startup_time, // \arg main osc startup time in microsecond (us) 01116 unsigned int slowClock) // \arg slowClock in Hz 01117 { 01118 pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; 01119 pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; 01120 } 01121 01122 //*---------------------------------------------------------------------------- 01123 //* \fn AT91F_CKGR_GetMainClockFreqReg 01124 //* \brief Cfg the main oscillator 01125 //*---------------------------------------------------------------------------- 01126 __inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( 01127 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 01128 { 01129 return pCKGR->CKGR_MCFR; 01130 } 01131 01132 //*---------------------------------------------------------------------------- 01133 //* \fn AT91F_CKGR_GetMainClock 01134 //* \brief Return Main clock in Hz 01135 //*---------------------------------------------------------------------------- 01136 __inline unsigned int AT91F_CKGR_GetMainClock ( 01137 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 01138 unsigned int slowClock) // \arg slowClock in Hz 01139 { 01140 return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; 01141 } 01142 01143 //*---------------------------------------------------------------------------- 01144 //* \fn AT91F_PMC_CfgMCKReg 01145 //* \brief Cfg Master Clock Register 01146 //*---------------------------------------------------------------------------- 01147 __inline void AT91F_PMC_CfgMCKReg ( 01148 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01149 unsigned int mode) 01150 { 01151 pPMC->PMC_MCKR = mode; 01152 } 01153 01154 //*---------------------------------------------------------------------------- 01155 //* \fn AT91F_PMC_GetMCKReg 01156 //* \brief Return Master Clock Register 01157 //*---------------------------------------------------------------------------- 01158 __inline unsigned int AT91F_PMC_GetMCKReg( 01159 AT91PS_PMC pPMC) // \arg pointer to PMC controller 01160 { 01161 return pPMC->PMC_MCKR; 01162 } 01163 01164 //*------------------------------------------------------------------------------ 01165 //* \fn AT91F_PMC_GetMasterClock 01166 //* \brief Return master clock in Hz which correponds to processor clock for ARM7 01167 //*------------------------------------------------------------------------------ 01168 __inline unsigned int AT91F_PMC_GetMasterClock ( 01169 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01170 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 01171 unsigned int slowClock) // \arg slowClock in Hz 01172 { 01173 unsigned int reg = pPMC->PMC_MCKR; 01174 unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); 01175 unsigned int pllDivider, pllMultiplier; 01176 01177 switch (reg & AT91C_PMC_CSS) { 01178 case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected 01179 return slowClock / prescaler; 01180 case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected 01181 return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; 01182 case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected 01183 reg = pCKGR->CKGR_PLLR; 01184 pllDivider = (reg & AT91C_CKGR_DIV); 01185 pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; 01186 return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; 01187 } 01188 return 0; 01189 } 01190 01191 //*---------------------------------------------------------------------------- 01192 //* \fn AT91F_PMC_EnablePCK 01193 //* \brief Enable peripheral clock 01194 //*---------------------------------------------------------------------------- 01195 __inline void AT91F_PMC_EnablePCK ( 01196 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01197 unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 01198 unsigned int mode) 01199 { 01200 pPMC->PMC_PCKR[pck] = mode; 01201 pPMC->PMC_SCER = (1 << pck) << 8; 01202 } 01203 01204 //*---------------------------------------------------------------------------- 01205 //* \fn AT91F_PMC_DisablePCK 01206 //* \brief Enable peripheral clock 01207 //*---------------------------------------------------------------------------- 01208 __inline void AT91F_PMC_DisablePCK ( 01209 AT91PS_PMC pPMC, // \arg pointer to PMC controller 01210 unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 01211 { 01212 pPMC->PMC_SCDR = (1 << pck) << 8; 01213 } 01214 01215 //*---------------------------------------------------------------------------- 01216 //* \fn AT91F_PMC_EnableIt 01217 //* \brief Enable PMC interrupt 01218 //*---------------------------------------------------------------------------- 01219 __inline void AT91F_PMC_EnableIt ( 01220 AT91PS_PMC pPMC, // pointer to a PMC controller 01221 unsigned int flag) // IT to be enabled 01222 { 01223 //* Write to the IER register 01224 pPMC->PMC_IER = flag; 01225 } 01226 01227 //*---------------------------------------------------------------------------- 01228 //* \fn AT91F_PMC_DisableIt 01229 //* \brief Disable PMC interrupt 01230 //*---------------------------------------------------------------------------- 01231 __inline void AT91F_PMC_DisableIt ( 01232 AT91PS_PMC pPMC, // pointer to a PMC controller 01233 unsigned int flag) // IT to be disabled 01234 { 01235 //* Write to the IDR register 01236 pPMC->PMC_IDR = flag; 01237 } 01238 01239 //*---------------------------------------------------------------------------- 01240 //* \fn AT91F_PMC_GetStatus 01241 //* \brief Return PMC Interrupt Status 01242 //*---------------------------------------------------------------------------- 01243 __inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status 01244 AT91PS_PMC pPMC) // pointer to a PMC controller 01245 { 01246 return pPMC->PMC_SR; 01247 } 01248 01249 //*---------------------------------------------------------------------------- 01250 //* \fn AT91F_PMC_GetInterruptMaskStatus 01251 //* \brief Return PMC Interrupt Mask Status 01252 //*---------------------------------------------------------------------------- 01253 __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status 01254 AT91PS_PMC pPMC) // pointer to a PMC controller 01255 { 01256 return pPMC->PMC_IMR; 01257 } 01258 01259 //*---------------------------------------------------------------------------- 01260 //* \fn AT91F_PMC_IsInterruptMasked 01261 //* \brief Test if PMC Interrupt is Masked 01262 //*---------------------------------------------------------------------------- 01263 __inline unsigned int AT91F_PMC_IsInterruptMasked( 01264 AT91PS_PMC pPMC, // \arg pointer to a PMC controller 01265 unsigned int flag) // \arg flag to be tested 01266 { 01267 return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); 01268 } 01269 01270 //*---------------------------------------------------------------------------- 01271 //* \fn AT91F_PMC_IsStatusSet 01272 //* \brief Test if PMC Status is Set 01273 //*---------------------------------------------------------------------------- 01274 __inline unsigned int AT91F_PMC_IsStatusSet( 01275 AT91PS_PMC pPMC, // \arg pointer to a PMC controller 01276 unsigned int flag) // \arg flag to be tested 01277 { 01278 return (AT91F_PMC_GetStatus(pPMC) & flag); 01279 }/* ***************************************************************************** 01280 SOFTWARE API FOR RSTC 01281 ***************************************************************************** */ 01282 //*---------------------------------------------------------------------------- 01283 //* \fn AT91F_RSTSoftReset 01284 //* \brief Start Software Reset 01285 //*---------------------------------------------------------------------------- 01286 __inline void AT91F_RSTSoftReset( 01287 AT91PS_RSTC pRSTC, 01288 unsigned int reset) 01289 { 01290 pRSTC->RSTC_RCR = (0xA5000000 | reset); 01291 } 01292 01293 //*---------------------------------------------------------------------------- 01294 //* \fn AT91F_RSTSetMode 01295 //* \brief Set Reset Mode 01296 //*---------------------------------------------------------------------------- 01297 __inline void AT91F_RSTSetMode( 01298 AT91PS_RSTC pRSTC, 01299 unsigned int mode) 01300 { 01301 pRSTC->RSTC_RMR = (0xA5000000 | mode); 01302 } 01303 01304 //*---------------------------------------------------------------------------- 01305 //* \fn AT91F_RSTGetMode 01306 //* \brief Get Reset Mode 01307 //*---------------------------------------------------------------------------- 01308 __inline unsigned int AT91F_RSTGetMode( 01309 AT91PS_RSTC pRSTC) 01310 { 01311 return (pRSTC->RSTC_RMR); 01312 } 01313 01314 //*---------------------------------------------------------------------------- 01315 //* \fn AT91F_RSTGetStatus 01316 //* \brief Get Reset Status 01317 //*---------------------------------------------------------------------------- 01318 __inline unsigned int AT91F_RSTGetStatus( 01319 AT91PS_RSTC pRSTC) 01320 { 01321 return (pRSTC->RSTC_RSR); 01322 } 01323 01324 //*---------------------------------------------------------------------------- 01325 //* \fn AT91F_RSTIsSoftRstActive 01326 //* \brief Return !=0 if software reset is still not completed 01327 //*---------------------------------------------------------------------------- 01328 __inline unsigned int AT91F_RSTIsSoftRstActive( 01329 AT91PS_RSTC pRSTC) 01330 { 01331 return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); 01332 } 01333 /* ***************************************************************************** 01334 SOFTWARE API FOR RTTC 01335 ***************************************************************************** */ 01336 //*-------------------------------------------------------------------------------------- 01337 //* \fn AT91F_SetRTT_TimeBase() 01338 //* \brief Set the RTT prescaler according to the TimeBase in ms 01339 //*-------------------------------------------------------------------------------------- 01340 __inline unsigned int AT91F_RTTSetTimeBase( 01341 AT91PS_RTTC pRTTC, 01342 unsigned int ms) 01343 { 01344 if (ms > 2000) 01345 return 1; // AT91C_TIME_OUT_OF_RANGE 01346 pRTTC->RTTC_RTMR &= ~0xFFFF; 01347 pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); 01348 return 0; 01349 } 01350 01351 //*-------------------------------------------------------------------------------------- 01352 //* \fn AT91F_RTTSetPrescaler() 01353 //* \brief Set the new prescaler value 01354 //*-------------------------------------------------------------------------------------- 01355 __inline unsigned int AT91F_RTTSetPrescaler( 01356 AT91PS_RTTC pRTTC, 01357 unsigned int rtpres) 01358 { 01359 pRTTC->RTTC_RTMR &= ~0xFFFF; 01360 pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); 01361 return (pRTTC->RTTC_RTMR); 01362 } 01363 01364 //*-------------------------------------------------------------------------------------- 01365 //* \fn AT91F_RTTRestart() 01366 //* \brief Restart the RTT prescaler 01367 //*-------------------------------------------------------------------------------------- 01368 __inline void AT91F_RTTRestart( 01369 AT91PS_RTTC pRTTC) 01370 { 01371 pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; 01372 } 01373 01374 01375 //*-------------------------------------------------------------------------------------- 01376 //* \fn AT91F_RTT_SetAlarmINT() 01377 //* \brief Enable RTT Alarm Interrupt 01378 //*-------------------------------------------------------------------------------------- 01379 __inline void AT91F_RTTSetAlarmINT( 01380 AT91PS_RTTC pRTTC) 01381 { 01382 pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; 01383 } 01384 01385 //*-------------------------------------------------------------------------------------- 01386 //* \fn AT91F_RTT_ClearAlarmINT() 01387 //* \brief Disable RTT Alarm Interrupt 01388 //*-------------------------------------------------------------------------------------- 01389 __inline void AT91F_RTTClearAlarmINT( 01390 AT91PS_RTTC pRTTC) 01391 { 01392 pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; 01393 } 01394 01395 //*-------------------------------------------------------------------------------------- 01396 //* \fn AT91F_RTT_SetRttIncINT() 01397 //* \brief Enable RTT INC Interrupt 01398 //*-------------------------------------------------------------------------------------- 01399 __inline void AT91F_RTTSetRttIncINT( 01400 AT91PS_RTTC pRTTC) 01401 { 01402 pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; 01403 } 01404 01405 //*-------------------------------------------------------------------------------------- 01406 //* \fn AT91F_RTT_ClearRttIncINT() 01407 //* \brief Disable RTT INC Interrupt 01408 //*-------------------------------------------------------------------------------------- 01409 __inline void AT91F_RTTClearRttIncINT( 01410 AT91PS_RTTC pRTTC) 01411 { 01412 pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; 01413 } 01414 01415 //*-------------------------------------------------------------------------------------- 01416 //* \fn AT91F_RTT_SetAlarmValue() 01417 //* \brief Set RTT Alarm Value 01418 //*-------------------------------------------------------------------------------------- 01419 __inline void AT91F_RTTSetAlarmValue( 01420 AT91PS_RTTC pRTTC, unsigned int alarm) 01421 { 01422 pRTTC->RTTC_RTAR = alarm; 01423 } 01424 01425 //*-------------------------------------------------------------------------------------- 01426 //* \fn AT91F_RTT_GetAlarmValue() 01427 //* \brief Get RTT Alarm Value 01428 //*-------------------------------------------------------------------------------------- 01429 __inline unsigned int AT91F_RTTGetAlarmValue( 01430 AT91PS_RTTC pRTTC) 01431 { 01432 return(pRTTC->RTTC_RTAR); 01433 } 01434 01435 //*-------------------------------------------------------------------------------------- 01436 //* \fn AT91F_RTTGetStatus() 01437 //* \brief Read the RTT status 01438 //*-------------------------------------------------------------------------------------- 01439 __inline unsigned int AT91F_RTTGetStatus( 01440 AT91PS_RTTC pRTTC) 01441 { 01442 return(pRTTC->RTTC_RTSR); 01443 } 01444 01445 //*-------------------------------------------------------------------------------------- 01446 //* \fn AT91F_RTT_ReadValue() 01447 //* \brief Read the RTT value 01448 //*-------------------------------------------------------------------------------------- 01449 __inline unsigned int AT91F_RTTReadValue( 01450 AT91PS_RTTC pRTTC) 01451 { 01452 register volatile unsigned int val1,val2; 01453 do 01454 { 01455 val1 = pRTTC->RTTC_RTVR; 01456 val2 = pRTTC->RTTC_RTVR; 01457 } 01458 while(val1 != val2); 01459 return(val1); 01460 } 01461 /* ***************************************************************************** 01462 SOFTWARE API FOR PITC 01463 ***************************************************************************** */ 01464 //*---------------------------------------------------------------------------- 01465 //* \fn AT91F_PITInit 01466 //* \brief System timer init : period in µsecond, system clock freq in MHz 01467 //*---------------------------------------------------------------------------- 01468 __inline void AT91F_PITInit( 01469 AT91PS_PITC pPITC, 01470 unsigned int period, 01471 unsigned int pit_frequency) 01472 { 01473 pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 01474 pPITC->PITC_PIMR |= AT91C_PITC_PITEN; 01475 } 01476 01477 //*---------------------------------------------------------------------------- 01478 //* \fn AT91F_PITSetPIV 01479 //* \brief Set the PIT Periodic Interval Value 01480 //*---------------------------------------------------------------------------- 01481 __inline void AT91F_PITSetPIV( 01482 AT91PS_PITC pPITC, 01483 unsigned int piv) 01484 { 01485 pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); 01486 } 01487 01488 //*---------------------------------------------------------------------------- 01489 //* \fn AT91F_PITEnableInt 01490 //* \brief Enable PIT periodic interrupt 01491 //*---------------------------------------------------------------------------- 01492 __inline void AT91F_PITEnableInt( 01493 AT91PS_PITC pPITC) 01494 { 01495 pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; 01496 } 01497 01498 //*---------------------------------------------------------------------------- 01499 //* \fn AT91F_PITDisableInt 01500 //* \brief Disable PIT periodic interrupt 01501 //*---------------------------------------------------------------------------- 01502 __inline void AT91F_PITDisableInt( 01503 AT91PS_PITC pPITC) 01504 { 01505 pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; 01506 } 01507 01508 //*---------------------------------------------------------------------------- 01509 //* \fn AT91F_PITGetMode 01510 //* \brief Read PIT mode register 01511 //*---------------------------------------------------------------------------- 01512 __inline unsigned int AT91F_PITGetMode( 01513 AT91PS_PITC pPITC) 01514 { 01515 return(pPITC->PITC_PIMR); 01516 } 01517 01518 //*---------------------------------------------------------------------------- 01519 //* \fn AT91F_PITGetStatus 01520 //* \brief Read PIT status register 01521 //*---------------------------------------------------------------------------- 01522 __inline unsigned int AT91F_PITGetStatus( 01523 AT91PS_PITC pPITC) 01524 { 01525 return(pPITC->PITC_PISR); 01526 } 01527 01528 //*---------------------------------------------------------------------------- 01529 //* \fn AT91F_PITGetPIIR 01530 //* \brief Read PIT CPIV and PICNT without ressetting the counters 01531 //*---------------------------------------------------------------------------- 01532 __inline unsigned int AT91F_PITGetPIIR( 01533 AT91PS_PITC pPITC) 01534 { 01535 return(pPITC->PITC_PIIR); 01536 } 01537 01538 //*---------------------------------------------------------------------------- 01539 //* \fn AT91F_PITGetPIVR 01540 //* \brief Read System timer CPIV and PICNT without ressetting the counters 01541 //*---------------------------------------------------------------------------- 01542 __inline unsigned int AT91F_PITGetPIVR( 01543 AT91PS_PITC pPITC) 01544 { 01545 return(pPITC->PITC_PIVR); 01546 } 01547 /* ***************************************************************************** 01548 SOFTWARE API FOR WDTC 01549 ***************************************************************************** */ 01550 //*---------------------------------------------------------------------------- 01551 //* \fn AT91F_WDTSetMode 01552 //* \brief Set Watchdog Mode Register 01553 //*---------------------------------------------------------------------------- 01554 __inline void AT91F_WDTSetMode( 01555 AT91PS_WDTC pWDTC, 01556 unsigned int Mode) 01557 { 01558 pWDTC->WDTC_WDMR = Mode; 01559 } 01560 01561 //*---------------------------------------------------------------------------- 01562 //* \fn AT91F_WDTRestart 01563 //* \brief Restart Watchdog 01564 //*---------------------------------------------------------------------------- 01565 __inline void AT91F_WDTRestart( 01566 AT91PS_WDTC pWDTC) 01567 { 01568 pWDTC->WDTC_WDCR = 0xA5000001; 01569 } 01570 01571 //*---------------------------------------------------------------------------- 01572 //* \fn AT91F_WDTSGettatus 01573 //* \brief Get Watchdog Status 01574 //*---------------------------------------------------------------------------- 01575 __inline unsigned int AT91F_WDTSGettatus( 01576 AT91PS_WDTC pWDTC) 01577 { 01578 return(pWDTC->WDTC_WDSR & 0x3); 01579 } 01580 01581 //*---------------------------------------------------------------------------- 01582 //* \fn AT91F_WDTGetPeriod 01583 //* \brief Translate ms into Watchdog Compatible value 01584 //*---------------------------------------------------------------------------- 01585 __inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) 01586 { 01587 if ((ms < 4) || (ms > 16000)) 01588 return 0; 01589 return((ms << 8) / 1000); 01590 } 01591 /* ***************************************************************************** 01592 SOFTWARE API FOR VREG 01593 ***************************************************************************** */ 01594 //*---------------------------------------------------------------------------- 01595 //* \fn AT91F_VREG_Enable_LowPowerMode 01596 //* \brief Enable VREG Low Power Mode 01597 //*---------------------------------------------------------------------------- 01598 __inline void AT91F_VREG_Enable_LowPowerMode( 01599 AT91PS_VREG pVREG) 01600 { 01601 pVREG->VREG_MR |= AT91C_VREG_PSTDBY; 01602 } 01603 01604 //*---------------------------------------------------------------------------- 01605 //* \fn AT91F_VREG_Disable_LowPowerMode 01606 //* \brief Disable VREG Low Power Mode 01607 //*---------------------------------------------------------------------------- 01608 __inline void AT91F_VREG_Disable_LowPowerMode( 01609 AT91PS_VREG pVREG) 01610 { 01611 pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; 01612 }/* ***************************************************************************** 01613 SOFTWARE API FOR MC 01614 ***************************************************************************** */ 01615 01616 #define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key 01617 01618 //*---------------------------------------------------------------------------- 01619 //* \fn AT91F_MC_Remap 01620 //* \brief Make Remap 01621 //*---------------------------------------------------------------------------- 01622 __inline void AT91F_MC_Remap (void) // 01623 { 01624 AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; 01625 01626 pMC->MC_RCR = AT91C_MC_RCB; 01627 } 01628 01629 //*---------------------------------------------------------------------------- 01630 //* \fn AT91F_MC_EFC_CfgModeReg 01631 //* \brief Configure the EFC Mode Register of the MC controller 01632 //*---------------------------------------------------------------------------- 01633 __inline void AT91F_MC_EFC_CfgModeReg ( 01634 AT91PS_MC pMC, // pointer to a MC controller 01635 unsigned int mode) // mode register 01636 { 01637 // Write to the FMR register 01638 pMC->MC_FMR = mode; 01639 } 01640 01641 //*---------------------------------------------------------------------------- 01642 //* \fn AT91F_MC_EFC_GetModeReg 01643 //* \brief Return MC EFC Mode Regsiter 01644 //*---------------------------------------------------------------------------- 01645 __inline unsigned int AT91F_MC_EFC_GetModeReg( 01646 AT91PS_MC pMC) // pointer to a MC controller 01647 { 01648 return pMC->MC_FMR; 01649 } 01650 01651 //*---------------------------------------------------------------------------- 01652 //* \fn AT91F_MC_EFC_ComputeFMCN 01653 //* \brief Return MC EFC Mode Regsiter 01654 //*---------------------------------------------------------------------------- 01655 __inline unsigned int AT91F_MC_EFC_ComputeFMCN( 01656 int master_clock) // master clock in Hz 01657 { 01658 return (master_clock/1000000 +2); 01659 } 01660 01661 //*---------------------------------------------------------------------------- 01662 //* \fn AT91F_MC_EFC_PerformCmd 01663 //* \brief Perform EFC Command 01664 //*---------------------------------------------------------------------------- 01665 __inline void AT91F_MC_EFC_PerformCmd ( 01666 AT91PS_MC pMC, // pointer to a MC controller 01667 unsigned int transfer_cmd) 01668 { 01669 pMC->MC_FCR = transfer_cmd; 01670 } 01671 01672 //*---------------------------------------------------------------------------- 01673 //* \fn AT91F_MC_EFC_GetStatus 01674 //* \brief Return MC EFC Status 01675 //*---------------------------------------------------------------------------- 01676 __inline unsigned int AT91F_MC_EFC_GetStatus( 01677 AT91PS_MC pMC) // pointer to a MC controller 01678 { 01679 return pMC->MC_FSR; 01680 } 01681 01682 //*---------------------------------------------------------------------------- 01683 //* \fn AT91F_MC_EFC_IsInterruptMasked 01684 //* \brief Test if EFC MC Interrupt is Masked 01685 //*---------------------------------------------------------------------------- 01686 __inline unsigned int AT91F_MC_EFC_IsInterruptMasked( 01687 AT91PS_MC pMC, // \arg pointer to a MC controller 01688 unsigned int flag) // \arg flag to be tested 01689 { 01690 return (AT91F_MC_EFC_GetModeReg(pMC) & flag); 01691 } 01692 01693 //*---------------------------------------------------------------------------- 01694 //* \fn AT91F_MC_EFC_IsInterruptSet 01695 //* \brief Test if EFC MC Interrupt is Set 01696 //*---------------------------------------------------------------------------- 01697 __inline unsigned int AT91F_MC_EFC_IsInterruptSet( 01698 AT91PS_MC pMC, // \arg pointer to a MC controller 01699 unsigned int flag) // \arg flag to be tested 01700 { 01701 return (AT91F_MC_EFC_GetStatus(pMC) & flag); 01702 } 01703 01704 /* ***************************************************************************** 01705 SOFTWARE API FOR SPI 01706 ***************************************************************************** */ 01707 //*---------------------------------------------------------------------------- 01708 //* \fn AT91F_SPI_Open 01709 //* \brief Open a SPI Port 01710 //*---------------------------------------------------------------------------- 01711 __inline unsigned int AT91F_SPI_Open ( 01712 const unsigned int null) // \arg 01713 { 01714 /* NOT DEFINED AT THIS MOMENT */ 01715 return ( 0 ); 01716 } 01717 01718 //*---------------------------------------------------------------------------- 01719 //* \fn AT91F_SPI_CfgCs 01720 //* \brief Configure SPI chip select register 01721 //*---------------------------------------------------------------------------- 01722 __inline void AT91F_SPI_CfgCs ( 01723 AT91PS_SPI pSPI, // pointer to a SPI controller 01724 int cs, // SPI cs number (0 to 3) 01725 int val) // chip select register 01726 { 01727 //* Write to the CSR register 01728 *(pSPI->SPI_CSR + cs) = val; 01729 } 01730 01731 //*---------------------------------------------------------------------------- 01732 //* \fn AT91F_SPI_EnableIt 01733 //* \brief Enable SPI interrupt 01734 //*---------------------------------------------------------------------------- 01735 __inline void AT91F_SPI_EnableIt ( 01736 AT91PS_SPI pSPI, // pointer to a SPI controller 01737 unsigned int flag) // IT to be enabled 01738 { 01739 //* Write to the IER register 01740 pSPI->SPI_IER = flag; 01741 } 01742 01743 //*---------------------------------------------------------------------------- 01744 //* \fn AT91F_SPI_DisableIt 01745 //* \brief Disable SPI interrupt 01746 //*---------------------------------------------------------------------------- 01747 __inline void AT91F_SPI_DisableIt ( 01748 AT91PS_SPI pSPI, // pointer to a SPI controller 01749 unsigned int flag) // IT to be disabled 01750 { 01751 //* Write to the IDR register 01752 pSPI->SPI_IDR = flag; 01753 } 01754 01755 //*---------------------------------------------------------------------------- 01756 //* \fn AT91F_SPI_Reset 01757 //* \brief Reset the SPI controller 01758 //*---------------------------------------------------------------------------- 01759 __inline void AT91F_SPI_Reset ( 01760 AT91PS_SPI pSPI // pointer to a SPI controller 01761 ) 01762 { 01763 //* Write to the CR register 01764 pSPI->SPI_CR = AT91C_SPI_SWRST; 01765 } 01766 01767 //*---------------------------------------------------------------------------- 01768 //* \fn AT91F_SPI_Enable 01769 //* \brief Enable the SPI controller 01770 //*---------------------------------------------------------------------------- 01771 __inline void AT91F_SPI_Enable ( 01772 AT91PS_SPI pSPI // pointer to a SPI controller 01773 ) 01774 { 01775 //* Write to the CR register 01776 pSPI->SPI_CR = AT91C_SPI_SPIEN; 01777 } 01778 01779 //*---------------------------------------------------------------------------- 01780 //* \fn AT91F_SPI_Disable 01781 //* \brief Disable the SPI controller 01782 //*---------------------------------------------------------------------------- 01783 __inline void AT91F_SPI_Disable ( 01784 AT91PS_SPI pSPI // pointer to a SPI controller 01785 ) 01786 { 01787 //* Write to the CR register 01788 pSPI->SPI_CR = AT91C_SPI_SPIDIS; 01789 } 01790 01791 //*---------------------------------------------------------------------------- 01792 //* \fn AT91F_SPI_CfgMode 01793 //* \brief Enable the SPI controller 01794 //*---------------------------------------------------------------------------- 01795 __inline void AT91F_SPI_CfgMode ( 01796 AT91PS_SPI pSPI, // pointer to a SPI controller 01797 int mode) // mode register 01798 { 01799 //* Write to the MR register 01800 pSPI->SPI_MR = mode; 01801 } 01802 01803 //*---------------------------------------------------------------------------- 01804 //* \fn AT91F_SPI_CfgPCS 01805 //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected 01806 //*---------------------------------------------------------------------------- 01807 __inline void AT91F_SPI_CfgPCS ( 01808 AT91PS_SPI pSPI, // pointer to a SPI controller 01809 char PCS_Device) // PCS of the Device 01810 { 01811 //* Write to the MR register 01812 pSPI->SPI_MR &= 0xFFF0FFFF; 01813 pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); 01814 } 01815 01816 //*---------------------------------------------------------------------------- 01817 //* \fn AT91F_SPI_ReceiveFrame 01818 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 01819 //*---------------------------------------------------------------------------- 01820 __inline unsigned int AT91F_SPI_ReceiveFrame ( 01821 AT91PS_SPI pSPI, 01822 char *pBuffer, 01823 unsigned int szBuffer, 01824 char *pNextBuffer, 01825 unsigned int szNextBuffer ) 01826 { 01827 return AT91F_PDC_ReceiveFrame( 01828 (AT91PS_PDC) &(pSPI->SPI_RPR), 01829 pBuffer, 01830 szBuffer, 01831 pNextBuffer, 01832 szNextBuffer); 01833 } 01834 01835 //*---------------------------------------------------------------------------- 01836 //* \fn AT91F_SPI_SendFrame 01837 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy 01838 //*---------------------------------------------------------------------------- 01839 __inline unsigned int AT91F_SPI_SendFrame( 01840 AT91PS_SPI pSPI, 01841 char *pBuffer, 01842 unsigned int szBuffer, 01843 char *pNextBuffer, 01844 unsigned int szNextBuffer ) 01845 { 01846 return AT91F_PDC_SendFrame( 01847 (AT91PS_PDC) &(pSPI->SPI_RPR), 01848 pBuffer, 01849 szBuffer, 01850 pNextBuffer, 01851 szNextBuffer); 01852 } 01853 01854 //*---------------------------------------------------------------------------- 01855 //* \fn AT91F_SPI_Close 01856 //* \brief Close SPI: disable IT disable transfert, close PDC 01857 //*---------------------------------------------------------------------------- 01858 __inline void AT91F_SPI_Close ( 01859 AT91PS_SPI pSPI) // \arg pointer to a SPI controller 01860 { 01861 //* Reset all the Chip Select register 01862 pSPI->SPI_CSR[0] = 0 ; 01863 pSPI->SPI_CSR[1] = 0 ; 01864 pSPI->SPI_CSR[2] = 0 ; 01865 pSPI->SPI_CSR[3] = 0 ; 01866 01867 //* Reset the SPI mode 01868 pSPI->SPI_MR = 0 ; 01869 01870 //* Disable all interrupts 01871 pSPI->SPI_IDR = 0xFFFFFFFF ; 01872 01873 //* Abort the Peripheral Data Transfers 01874 AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); 01875 01876 //* Disable receiver and transmitter and stop any activity immediately 01877 pSPI->SPI_CR = AT91C_SPI_SPIDIS; 01878 } 01879 01880 //*---------------------------------------------------------------------------- 01881 //* \fn AT91F_SPI_PutChar 01882 //* \brief Send a character,does not check if ready to send 01883 //*---------------------------------------------------------------------------- 01884 __inline void AT91F_SPI_PutChar ( 01885 AT91PS_SPI pSPI, 01886 unsigned int character, 01887 unsigned int cs_number ) 01888 { 01889 unsigned int value_for_cs; 01890 value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number 01891 pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); 01892 } 01893 01894 //*---------------------------------------------------------------------------- 01895 //* \fn AT91F_SPI_GetChar 01896 //* \brief Receive a character,does not check if a character is available 01897 //*---------------------------------------------------------------------------- 01898 __inline int AT91F_SPI_GetChar ( 01899 const AT91PS_SPI pSPI) 01900 { 01901 return((pSPI->SPI_RDR) & 0xFFFF); 01902 } 01903 01904 //*---------------------------------------------------------------------------- 01905 //* \fn AT91F_SPI_GetInterruptMaskStatus 01906 //* \brief Return SPI Interrupt Mask Status 01907 //*---------------------------------------------------------------------------- 01908 __inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status 01909 AT91PS_SPI pSpi) // \arg pointer to a SPI controller 01910 { 01911 return pSpi->SPI_IMR; 01912 } 01913 01914 //*---------------------------------------------------------------------------- 01915 //* \fn AT91F_SPI_IsInterruptMasked 01916 //* \brief Test if SPI Interrupt is Masked 01917 //*---------------------------------------------------------------------------- 01918 __inline int AT91F_SPI_IsInterruptMasked( 01919 AT91PS_SPI pSpi, // \arg pointer to a SPI controller 01920 unsigned int flag) // \arg flag to be tested 01921 { 01922 return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); 01923 } 01924 01925 /* ***************************************************************************** 01926 SOFTWARE API FOR ADC 01927 ***************************************************************************** */ 01928 //*---------------------------------------------------------------------------- 01929 //* \fn AT91F_ADC_EnableIt 01930 //* \brief Enable ADC interrupt 01931 //*---------------------------------------------------------------------------- 01932 __inline void AT91F_ADC_EnableIt ( 01933 AT91PS_ADC pADC, // pointer to a ADC controller 01934 unsigned int flag) // IT to be enabled 01935 { 01936 //* Write to the IER register 01937 pADC->ADC_IER = flag; 01938 } 01939 01940 //*---------------------------------------------------------------------------- 01941 //* \fn AT91F_ADC_DisableIt 01942 //* \brief Disable ADC interrupt 01943 //*---------------------------------------------------------------------------- 01944 __inline void AT91F_ADC_DisableIt ( 01945 AT91PS_ADC pADC, // pointer to a ADC controller 01946 unsigned int flag) // IT to be disabled 01947 { 01948 //* Write to the IDR register 01949 pADC->ADC_IDR = flag; 01950 } 01951 01952 //*---------------------------------------------------------------------------- 01953 //* \fn AT91F_ADC_GetStatus 01954 //* \brief Return ADC Interrupt Status 01955 //*---------------------------------------------------------------------------- 01956 __inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status 01957 AT91PS_ADC pADC) // pointer to a ADC controller 01958 { 01959 return pADC->ADC_SR; 01960 } 01961 01962 //*---------------------------------------------------------------------------- 01963 //* \fn AT91F_ADC_GetInterruptMaskStatus 01964 //* \brief Return ADC Interrupt Mask Status 01965 //*---------------------------------------------------------------------------- 01966 __inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status 01967 AT91PS_ADC pADC) // pointer to a ADC controller 01968 { 01969 return pADC->ADC_IMR; 01970 } 01971 01972 //*---------------------------------------------------------------------------- 01973 //* \fn AT91F_ADC_IsInterruptMasked 01974 //* \brief Test if ADC Interrupt is Masked 01975 //*---------------------------------------------------------------------------- 01976 __inline unsigned int AT91F_ADC_IsInterruptMasked( 01977 AT91PS_ADC pADC, // \arg pointer to a ADC controller 01978 unsigned int flag) // \arg flag to be tested 01979 { 01980 return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); 01981 } 01982 01983 //*---------------------------------------------------------------------------- 01984 //* \fn AT91F_ADC_IsStatusSet 01985 //* \brief Test if ADC Status is Set 01986 //*---------------------------------------------------------------------------- 01987 __inline unsigned int AT91F_ADC_IsStatusSet( 01988 AT91PS_ADC pADC, // \arg pointer to a ADC controller 01989 unsigned int flag) // \arg flag to be tested 01990 { 01991 return (AT91F_ADC_GetStatus(pADC) & flag); 01992 } 01993 01994 //*---------------------------------------------------------------------------- 01995 //* \fn AT91F_ADC_CfgModeReg 01996 //* \brief Configure the Mode Register of the ADC controller 01997 //*---------------------------------------------------------------------------- 01998 __inline void AT91F_ADC_CfgModeReg ( 01999 AT91PS_ADC pADC, // pointer to a ADC controller 02000 unsigned int mode) // mode register 02001 { 02002 //* Write to the MR register 02003 pADC->ADC_MR = mode; 02004 } 02005 02006 //*---------------------------------------------------------------------------- 02007 //* \fn AT91F_ADC_GetModeReg 02008 //* \brief Return the Mode Register of the ADC controller value 02009 //*---------------------------------------------------------------------------- 02010 __inline unsigned int AT91F_ADC_GetModeReg ( 02011 AT91PS_ADC pADC // pointer to a ADC controller 02012 ) 02013 { 02014 return pADC->ADC_MR; 02015 } 02016 02017 //*---------------------------------------------------------------------------- 02018 //* \fn AT91F_ADC_CfgTimings 02019 //* \brief Configure the different necessary timings of the ADC controller 02020 //*---------------------------------------------------------------------------- 02021 __inline void AT91F_ADC_CfgTimings ( 02022 AT91PS_ADC pADC, // pointer to a ADC controller 02023 unsigned int mck_clock, // in MHz 02024 unsigned int adc_clock, // in MHz 02025 unsigned int startup_time, // in us 02026 unsigned int sample_and_hold_time) // in ns 02027 { 02028 unsigned int prescal,startup,shtim; 02029 02030 prescal = mck_clock/(2*adc_clock) - 1; 02031 startup = adc_clock*startup_time/8 - 1; 02032 shtim = adc_clock*sample_and_hold_time/1000 - 1; 02033 02034 //* Write to the MR register 02035 pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); 02036 } 02037 02038 //*---------------------------------------------------------------------------- 02039 //* \fn AT91F_ADC_EnableChannel 02040 //* \brief Return ADC Timer Register Value 02041 //*---------------------------------------------------------------------------- 02042 __inline void AT91F_ADC_EnableChannel ( 02043 AT91PS_ADC pADC, // pointer to a ADC controller 02044 unsigned int channel) // mode register 02045 { 02046 //* Write to the CHER register 02047 pADC->ADC_CHER = channel; 02048 } 02049 02050 //*---------------------------------------------------------------------------- 02051 //* \fn AT91F_ADC_DisableChannel 02052 //* \brief Return ADC Timer Register Value 02053 //*---------------------------------------------------------------------------- 02054 __inline void AT91F_ADC_DisableChannel ( 02055 AT91PS_ADC pADC, // pointer to a ADC controller 02056 unsigned int channel) // mode register 02057 { 02058 //* Write to the CHDR register 02059 pADC->ADC_CHDR = channel; 02060 } 02061 02062 //*---------------------------------------------------------------------------- 02063 //* \fn AT91F_ADC_GetChannelStatus 02064 //* \brief Return ADC Timer Register Value 02065 //*---------------------------------------------------------------------------- 02066 __inline unsigned int AT91F_ADC_GetChannelStatus ( 02067 AT91PS_ADC pADC // pointer to a ADC controller 02068 ) 02069 { 02070 return pADC->ADC_CHSR; 02071 } 02072 02073 //*---------------------------------------------------------------------------- 02074 //* \fn AT91F_ADC_StartConversion 02075 //* \brief Software request for a analog to digital conversion 02076 //*---------------------------------------------------------------------------- 02077 __inline void AT91F_ADC_StartConversion ( 02078 AT91PS_ADC pADC // pointer to a ADC controller 02079 ) 02080 { 02081 pADC->ADC_CR = AT91C_ADC_START; 02082 } 02083 02084 //*---------------------------------------------------------------------------- 02085 //* \fn AT91F_ADC_SoftReset 02086 //* \brief Software reset 02087 //*---------------------------------------------------------------------------- 02088 __inline void AT91F_ADC_SoftReset ( 02089 AT91PS_ADC pADC // pointer to a ADC controller 02090 ) 02091 { 02092 pADC->ADC_CR = AT91C_ADC_SWRST; 02093 } 02094 02095 //*---------------------------------------------------------------------------- 02096 //* \fn AT91F_ADC_GetLastConvertedData 02097 //* \brief Return the Last Converted Data 02098 //*---------------------------------------------------------------------------- 02099 __inline unsigned int AT91F_ADC_GetLastConvertedData ( 02100 AT91PS_ADC pADC // pointer to a ADC controller 02101 ) 02102 { 02103 return pADC->ADC_LCDR; 02104 } 02105 02106 //*---------------------------------------------------------------------------- 02107 //* \fn AT91F_ADC_GetConvertedDataCH0 02108 //* \brief Return the Channel 0 Converted Data 02109 //*---------------------------------------------------------------------------- 02110 __inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( 02111 AT91PS_ADC pADC // pointer to a ADC controller 02112 ) 02113 { 02114 return pADC->ADC_CDR0; 02115 } 02116 02117 //*---------------------------------------------------------------------------- 02118 //* \fn AT91F_ADC_GetConvertedDataCH1 02119 //* \brief Return the Channel 1 Converted Data 02120 //*---------------------------------------------------------------------------- 02121 __inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( 02122 AT91PS_ADC pADC // pointer to a ADC controller 02123 ) 02124 { 02125 return pADC->ADC_CDR1; 02126 } 02127 02128 //*---------------------------------------------------------------------------- 02129 //* \fn AT91F_ADC_GetConvertedDataCH2 02130 //* \brief Return the Channel 2 Converted Data 02131 //*---------------------------------------------------------------------------- 02132 __inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( 02133 AT91PS_ADC pADC // pointer to a ADC controller 02134 ) 02135 { 02136 return pADC->ADC_CDR2; 02137 } 02138 02139 //*---------------------------------------------------------------------------- 02140 //* \fn AT91F_ADC_GetConvertedDataCH3 02141 //* \brief Return the Channel 3 Converted Data 02142 //*---------------------------------------------------------------------------- 02143 __inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( 02144 AT91PS_ADC pADC // pointer to a ADC controller 02145 ) 02146 { 02147 return pADC->ADC_CDR3; 02148 } 02149 02150 //*---------------------------------------------------------------------------- 02151 //* \fn AT91F_ADC_GetConvertedDataCH4 02152 //* \brief Return the Channel 4 Converted Data 02153 //*---------------------------------------------------------------------------- 02154 __inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( 02155 AT91PS_ADC pADC // pointer to a ADC controller 02156 ) 02157 { 02158 return pADC->ADC_CDR4; 02159 } 02160 02161 //*---------------------------------------------------------------------------- 02162 //* \fn AT91F_ADC_GetConvertedDataCH5 02163 //* \brief Return the Channel 5 Converted Data 02164 //*---------------------------------------------------------------------------- 02165 __inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( 02166 AT91PS_ADC pADC // pointer to a ADC controller 02167 ) 02168 { 02169 return pADC->ADC_CDR5; 02170 } 02171 02172 //*---------------------------------------------------------------------------- 02173 //* \fn AT91F_ADC_GetConvertedDataCH6 02174 //* \brief Return the Channel 6 Converted Data 02175 //*---------------------------------------------------------------------------- 02176 __inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( 02177 AT91PS_ADC pADC // pointer to a ADC controller 02178 ) 02179 { 02180 return pADC->ADC_CDR6; 02181 } 02182 02183 //*---------------------------------------------------------------------------- 02184 //* \fn AT91F_ADC_GetConvertedDataCH7 02185 //* \brief Return the Channel 7 Converted Data 02186 //*---------------------------------------------------------------------------- 02187 __inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( 02188 AT91PS_ADC pADC // pointer to a ADC controller 02189 ) 02190 { 02191 return pADC->ADC_CDR7; 02192 } 02193 02194 /* ***************************************************************************** 02195 SOFTWARE API FOR SSC 02196 ***************************************************************************** */ 02197 //* Define the standard I2S mode configuration 02198 02199 //* Configuration to set in the SSC Transmit Clock Mode Register 02200 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits 02201 //* nb_slot_by_frame : number of channels 02202 #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ 02203 AT91C_SSC_CKS_DIV +\ 02204 AT91C_SSC_CKO_CONTINOUS +\ 02205 AT91C_SSC_CKG_NONE +\ 02206 AT91C_SSC_START_FALL_RF +\ 02207 AT91C_SSC_STTOUT +\ 02208 ((1<<16) & AT91C_SSC_STTDLY) +\ 02209 ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) 02210 02211 02212 //* Configuration to set in the SSC Transmit Frame Mode Register 02213 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits 02214 //* nb_slot_by_frame : number of channels 02215 #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ 02216 (nb_bit_by_slot-1) +\ 02217 AT91C_SSC_MSBF +\ 02218 (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ 02219 (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ 02220 AT91C_SSC_FSOS_NEGATIVE) 02221 02222 02223 //*---------------------------------------------------------------------------- 02224 //* \fn AT91F_SSC_SetBaudrate 02225 //* \brief Set the baudrate according to the CPU clock 02226 //*---------------------------------------------------------------------------- 02227 __inline void AT91F_SSC_SetBaudrate ( 02228 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 02229 unsigned int mainClock, // \arg peripheral clock 02230 unsigned int speed) // \arg SSC baudrate 02231 { 02232 unsigned int baud_value; 02233 //* Define the baud rate divisor register 02234 if (speed == 0) 02235 baud_value = 0; 02236 else 02237 { 02238 baud_value = (unsigned int) (mainClock * 10)/(2*speed); 02239 if ((baud_value % 10) >= 5) 02240 baud_value = (baud_value / 10) + 1; 02241 else 02242 baud_value /= 10; 02243 } 02244 02245 pSSC->SSC_CMR = baud_value; 02246 } 02247 02248 //*---------------------------------------------------------------------------- 02249 //* \fn AT91F_SSC_Configure 02250 //* \brief Configure SSC 02251 //*---------------------------------------------------------------------------- 02252 __inline void AT91F_SSC_Configure ( 02253 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 02254 unsigned int syst_clock, // \arg System Clock Frequency 02255 unsigned int baud_rate, // \arg Expected Baud Rate Frequency 02256 unsigned int clock_rx, // \arg Receiver Clock Parameters 02257 unsigned int mode_rx, // \arg mode Register to be programmed 02258 unsigned int clock_tx, // \arg Transmitter Clock Parameters 02259 unsigned int mode_tx) // \arg mode Register to be programmed 02260 { 02261 //* Disable interrupts 02262 pSSC->SSC_IDR = (unsigned int) -1; 02263 02264 //* Reset receiver and transmitter 02265 pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; 02266 02267 //* Define the Clock Mode Register 02268 AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); 02269 02270 //* Write the Receive Clock Mode Register 02271 pSSC->SSC_RCMR = clock_rx; 02272 02273 //* Write the Transmit Clock Mode Register 02274 pSSC->SSC_TCMR = clock_tx; 02275 02276 //* Write the Receive Frame Mode Register 02277 pSSC->SSC_RFMR = mode_rx; 02278 02279 //* Write the Transmit Frame Mode Register 02280 pSSC->SSC_TFMR = mode_tx; 02281 02282 //* Clear Transmit and Receive Counters 02283 AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); 02284 02285 02286 } 02287 02288 //*---------------------------------------------------------------------------- 02289 //* \fn AT91F_SSC_EnableRx 02290 //* \brief Enable receiving datas 02291 //*---------------------------------------------------------------------------- 02292 __inline void AT91F_SSC_EnableRx ( 02293 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 02294 { 02295 //* Enable receiver 02296 pSSC->SSC_CR = AT91C_SSC_RXEN; 02297 } 02298 02299 //*---------------------------------------------------------------------------- 02300 //* \fn AT91F_SSC_DisableRx 02301 //* \brief Disable receiving datas 02302 //*---------------------------------------------------------------------------- 02303 __inline void AT91F_SSC_DisableRx ( 02304 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 02305 { 02306 //* Disable receiver 02307 pSSC->SSC_CR = AT91C_SSC_RXDIS; 02308 } 02309 02310 //*---------------------------------------------------------------------------- 02311 //* \fn AT91F_SSC_EnableTx 02312 //* \brief Enable sending datas 02313 //*---------------------------------------------------------------------------- 02314 __inline void AT91F_SSC_EnableTx ( 02315 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 02316 { 02317 //* Enable transmitter 02318 pSSC->SSC_CR = AT91C_SSC_TXEN; 02319 } 02320 02321 //*---------------------------------------------------------------------------- 02322 //* \fn AT91F_SSC_DisableTx 02323 //* \brief Disable sending datas 02324 //*---------------------------------------------------------------------------- 02325 __inline void AT91F_SSC_DisableTx ( 02326 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 02327 { 02328 //* Disable transmitter 02329 pSSC->SSC_CR = AT91C_SSC_TXDIS; 02330 } 02331 02332 //*---------------------------------------------------------------------------- 02333 //* \fn AT91F_SSC_EnableIt 02334 //* \brief Enable SSC IT 02335 //*---------------------------------------------------------------------------- 02336 __inline void AT91F_SSC_EnableIt ( 02337 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 02338 unsigned int flag) // \arg IT to be enabled 02339 { 02340 //* Write to the IER register 02341 pSSC->SSC_IER = flag; 02342 } 02343 02344 //*---------------------------------------------------------------------------- 02345 //* \fn AT91F_SSC_DisableIt 02346 //* \brief Disable SSC IT 02347 //*---------------------------------------------------------------------------- 02348 __inline void AT91F_SSC_DisableIt ( 02349 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 02350 unsigned int flag) // \arg IT to be disabled 02351 { 02352 //* Write to the IDR register 02353 pSSC->SSC_IDR = flag; 02354 } 02355 02356 //*---------------------------------------------------------------------------- 02357 //* \fn AT91F_SSC_ReceiveFrame 02358 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy 02359 //*---------------------------------------------------------------------------- 02360 __inline unsigned int AT91F_SSC_ReceiveFrame ( 02361 AT91PS_SSC pSSC, 02362 char *pBuffer, 02363 unsigned int szBuffer, 02364 char *pNextBuffer, 02365 unsigned int szNextBuffer ) 02366 { 02367 return AT91F_PDC_ReceiveFrame( 02368 (AT91PS_PDC) &(pSSC->SSC_RPR), 02369 pBuffer, 02370 szBuffer, 02371 pNextBuffer, 02372 szNextBuffer); 02373 } 02374 02375 //*---------------------------------------------------------------------------- 02376 //* \fn AT91F_SSC_SendFrame 02377 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy 02378 //*---------------------------------------------------------------------------- 02379 __inline unsigned int AT91F_SSC_SendFrame( 02380 AT91PS_SSC pSSC, 02381 char *pBuffer, 02382 unsigned int szBuffer, 02383 char *pNextBuffer, 02384 unsigned int szNextBuffer ) 02385 { 02386 return AT91F_PDC_SendFrame( 02387 (AT91PS_PDC) &(pSSC->SSC_RPR), 02388 pBuffer, 02389 szBuffer, 02390 pNextBuffer, 02391 szNextBuffer); 02392 } 02393 02394 //*---------------------------------------------------------------------------- 02395 //* \fn AT91F_SSC_GetInterruptMaskStatus 02396 //* \brief Return SSC Interrupt Mask Status 02397 //*---------------------------------------------------------------------------- 02398 __inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status 02399 AT91PS_SSC pSsc) // \arg pointer to a SSC controller 02400 { 02401 return pSsc->SSC_IMR; 02402 } 02403 02404 //*---------------------------------------------------------------------------- 02405 //* \fn AT91F_SSC_IsInterruptMasked 02406 //* \brief Test if SSC Interrupt is Masked 02407 //*---------------------------------------------------------------------------- 02408 __inline int AT91F_SSC_IsInterruptMasked( 02409 AT91PS_SSC pSsc, // \arg pointer to a SSC controller 02410 unsigned int flag) // \arg flag to be tested 02411 { 02412 return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); 02413 } 02414 02415 /* ***************************************************************************** 02416 SOFTWARE API FOR USART 02417 ***************************************************************************** */ 02418 //*---------------------------------------------------------------------------- 02419 //* \fn AT91F_US_Baudrate 02420 //* \brief Calculate the baudrate 02421 //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity 02422 #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ 02423 AT91C_US_NBSTOP_1_BIT + \ 02424 AT91C_US_PAR_NONE + \ 02425 AT91C_US_CHRL_8_BITS + \ 02426 AT91C_US_CLKS_CLOCK ) 02427 02428 //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity 02429 #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ 02430 AT91C_US_NBSTOP_1_BIT + \ 02431 AT91C_US_PAR_NONE + \ 02432 AT91C_US_CHRL_8_BITS + \ 02433 AT91C_US_CLKS_EXT ) 02434 02435 //* Standard Synchronous Mode : 8 bits , 1 stop , no parity 02436 #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ 02437 AT91C_US_USMODE_NORMAL + \ 02438 AT91C_US_NBSTOP_1_BIT + \ 02439 AT91C_US_PAR_NONE + \ 02440 AT91C_US_CHRL_8_BITS + \ 02441 AT91C_US_CLKS_CLOCK ) 02442 02443 //* SCK used Label 02444 #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) 02445 02446 //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity 02447 #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ 02448 AT91C_US_CLKS_CLOCK +\ 02449 AT91C_US_NBSTOP_1_BIT + \ 02450 AT91C_US_PAR_EVEN + \ 02451 AT91C_US_CHRL_8_BITS + \ 02452 AT91C_US_CKLO +\ 02453 AT91C_US_OVER) 02454 02455 //* Standard IRDA mode 02456 #define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ 02457 AT91C_US_NBSTOP_1_BIT + \ 02458 AT91C_US_PAR_NONE + \ 02459 AT91C_US_CHRL_8_BITS + \ 02460 AT91C_US_CLKS_CLOCK ) 02461 02462 //*---------------------------------------------------------------------------- 02463 //* \fn AT91F_US_Baudrate 02464 //* \brief Caluculate baud_value according to the main clock and the baud rate 02465 //*---------------------------------------------------------------------------- 02466 __inline unsigned int AT91F_US_Baudrate ( 02467 const unsigned int main_clock, // \arg peripheral clock 02468 const unsigned int baud_rate) // \arg UART baudrate 02469 { 02470 unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); 02471 if ((baud_value % 10) >= 5) 02472 baud_value = (baud_value / 10) + 1; 02473 else 02474 baud_value /= 10; 02475 return baud_value; 02476 } 02477 02478 //*---------------------------------------------------------------------------- 02479 //* \fn AT91F_US_SetBaudrate 02480 //* \brief Set the baudrate according to the CPU clock 02481 //*---------------------------------------------------------------------------- 02482 __inline void AT91F_US_SetBaudrate ( 02483 AT91PS_USART pUSART, // \arg pointer to a USART controller 02484 unsigned int mainClock, // \arg peripheral clock 02485 unsigned int speed) // \arg UART baudrate 02486 { 02487 //* Define the baud rate divisor register 02488 pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); 02489 } 02490 02491 //*---------------------------------------------------------------------------- 02492 //* \fn AT91F_US_SetTimeguard 02493 //* \brief Set USART timeguard 02494 //*---------------------------------------------------------------------------- 02495 __inline void AT91F_US_SetTimeguard ( 02496 AT91PS_USART pUSART, // \arg pointer to a USART controller 02497 unsigned int timeguard) // \arg timeguard value 02498 { 02499 //* Write the Timeguard Register 02500 pUSART->US_TTGR = timeguard ; 02501 } 02502 02503 //*---------------------------------------------------------------------------- 02504 //* \fn AT91F_US_EnableIt 02505 //* \brief Enable USART IT 02506 //*---------------------------------------------------------------------------- 02507 __inline void AT91F_US_EnableIt ( 02508 AT91PS_USART pUSART, // \arg pointer to a USART controller 02509 unsigned int flag) // \arg IT to be enabled 02510 { 02511 //* Write to the IER register 02512 pUSART->US_IER = flag; 02513 } 02514 02515 //*---------------------------------------------------------------------------- 02516 //* \fn AT91F_US_DisableIt 02517 //* \brief Disable USART IT 02518 //*---------------------------------------------------------------------------- 02519 __inline void AT91F_US_DisableIt ( 02520 AT91PS_USART pUSART, // \arg pointer to a USART controller 02521 unsigned int flag) // \arg IT to be disabled 02522 { 02523 //* Write to the IER register 02524 pUSART->US_IDR = flag; 02525 } 02526 02527 //*---------------------------------------------------------------------------- 02528 //* \fn AT91F_US_Configure 02529 //* \brief Configure USART 02530 //*---------------------------------------------------------------------------- 02531 __inline void AT91F_US_Configure ( 02532 AT91PS_USART pUSART, // \arg pointer to a USART controller 02533 unsigned int mainClock, // \arg peripheral clock 02534 unsigned int mode , // \arg mode Register to be programmed 02535 unsigned int baudRate , // \arg baudrate to be programmed 02536 unsigned int timeguard ) // \arg timeguard to be programmed 02537 { 02538 //* Disable interrupts 02539 pUSART->US_IDR = (unsigned int) -1; 02540 02541 //* Reset receiver and transmitter 02542 pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; 02543 02544 //* Define the baud rate divisor register 02545 AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); 02546 02547 //* Write the Timeguard Register 02548 AT91F_US_SetTimeguard(pUSART, timeguard); 02549 02550 //* Clear Transmit and Receive Counters 02551 AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); 02552 02553 //* Define the USART mode 02554 pUSART->US_MR = mode ; 02555 02556 } 02557 02558 //*---------------------------------------------------------------------------- 02559 //* \fn AT91F_US_EnableRx 02560 //* \brief Enable receiving characters 02561 //*---------------------------------------------------------------------------- 02562 __inline void AT91F_US_EnableRx ( 02563 AT91PS_USART pUSART) // \arg pointer to a USART controller 02564 { 02565 //* Enable receiver 02566 pUSART->US_CR = AT91C_US_RXEN; 02567 } 02568 02569 //*---------------------------------------------------------------------------- 02570 //* \fn AT91F_US_EnableTx 02571 //* \brief Enable sending characters 02572 //*---------------------------------------------------------------------------- 02573 __inline void AT91F_US_EnableTx ( 02574 AT91PS_USART pUSART) // \arg pointer to a USART controller 02575 { 02576 //* Enable transmitter 02577 pUSART->US_CR = AT91C_US_TXEN; 02578 } 02579 02580 //*---------------------------------------------------------------------------- 02581 //* \fn AT91F_US_ResetRx 02582 //* \brief Reset Receiver and re-enable it 02583 //*---------------------------------------------------------------------------- 02584 __inline void AT91F_US_ResetRx ( 02585 AT91PS_USART pUSART) // \arg pointer to a USART controller 02586 { 02587 //* Reset receiver 02588 pUSART->US_CR = AT91C_US_RSTRX; 02589 //* Re-Enable receiver 02590 pUSART->US_CR = AT91C_US_RXEN; 02591 } 02592 02593 //*---------------------------------------------------------------------------- 02594 //* \fn AT91F_US_ResetTx 02595 //* \brief Reset Transmitter and re-enable it 02596 //*---------------------------------------------------------------------------- 02597 __inline void AT91F_US_ResetTx ( 02598 AT91PS_USART pUSART) // \arg pointer to a USART controller 02599 { 02600 //* Reset transmitter 02601 pUSART->US_CR = AT91C_US_RSTTX; 02602 //* Enable transmitter 02603 pUSART->US_CR = AT91C_US_TXEN; 02604 } 02605 02606 //*---------------------------------------------------------------------------- 02607 //* \fn AT91F_US_DisableRx 02608 //* \brief Disable Receiver 02609 //*---------------------------------------------------------------------------- 02610 __inline void AT91F_US_DisableRx ( 02611 AT91PS_USART pUSART) // \arg pointer to a USART controller 02612 { 02613 //* Disable receiver 02614 pUSART->US_CR = AT91C_US_RXDIS; 02615 } 02616 02617 //*---------------------------------------------------------------------------- 02618 //* \fn AT91F_US_DisableTx 02619 //* \brief Disable Transmitter 02620 //*---------------------------------------------------------------------------- 02621 __inline void AT91F_US_DisableTx ( 02622 AT91PS_USART pUSART) // \arg pointer to a USART controller 02623 { 02624 //* Disable transmitter 02625 pUSART->US_CR = AT91C_US_TXDIS; 02626 } 02627 02628 //*---------------------------------------------------------------------------- 02629 //* \fn AT91F_US_Close 02630 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC 02631 //*---------------------------------------------------------------------------- 02632 __inline void AT91F_US_Close ( 02633 AT91PS_USART pUSART) // \arg pointer to a USART controller 02634 { 02635 //* Reset the baud rate divisor register 02636 pUSART->US_BRGR = 0 ; 02637 02638 //* Reset the USART mode 02639 pUSART->US_MR = 0 ; 02640 02641 //* Reset the Timeguard Register 02642 pUSART->US_TTGR = 0; 02643 02644 //* Disable all interrupts 02645 pUSART->US_IDR = 0xFFFFFFFF ; 02646 02647 //* Abort the Peripheral Data Transfers 02648 AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); 02649 02650 //* Disable receiver and transmitter and stop any activity immediately 02651 pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; 02652 } 02653 02654 //*---------------------------------------------------------------------------- 02655 //* \fn AT91F_US_TxReady 02656 //* \brief Return 1 if a character can be written in US_THR 02657 //*---------------------------------------------------------------------------- 02658 __inline unsigned int AT91F_US_TxReady ( 02659 AT91PS_USART pUSART ) // \arg pointer to a USART controller 02660 { 02661 return (pUSART->US_CSR & AT91C_US_TXRDY); 02662 } 02663 02664 //*---------------------------------------------------------------------------- 02665 //* \fn AT91F_US_RxReady 02666 //* \brief Return 1 if a character can be read in US_RHR 02667 //*---------------------------------------------------------------------------- 02668 __inline unsigned int AT91F_US_RxReady ( 02669 AT91PS_USART pUSART ) // \arg pointer to a USART controller 02670 { 02671 return (pUSART->US_CSR & AT91C_US_RXRDY); 02672 } 02673 02674 //*---------------------------------------------------------------------------- 02675 //* \fn AT91F_US_Error 02676 //* \brief Return the error flag 02677 //*---------------------------------------------------------------------------- 02678 __inline unsigned int AT91F_US_Error ( 02679 AT91PS_USART pUSART ) // \arg pointer to a USART controller 02680 { 02681 return (pUSART->US_CSR & 02682 (AT91C_US_OVRE | // Overrun error 02683 AT91C_US_FRAME | // Framing error 02684 AT91C_US_PARE)); // Parity error 02685 } 02686 02687 //*---------------------------------------------------------------------------- 02688 //* \fn AT91F_US_PutChar 02689 //* \brief Send a character,does not check if ready to send 02690 //*---------------------------------------------------------------------------- 02691 __inline void AT91F_US_PutChar ( 02692 AT91PS_USART pUSART, 02693 int character ) 02694 { 02695 pUSART->US_THR = (character & 0x1FF); 02696 } 02697 02698 //*---------------------------------------------------------------------------- 02699 //* \fn AT91F_US_GetChar 02700 //* \brief Receive a character,does not check if a character is available 02701 //*---------------------------------------------------------------------------- 02702 __inline int AT91F_US_GetChar ( 02703 const AT91PS_USART pUSART) 02704 { 02705 return((pUSART->US_RHR) & 0x1FF); 02706 } 02707 02708 //*---------------------------------------------------------------------------- 02709 //* \fn AT91F_US_SendFrame 02710 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 02711 //*---------------------------------------------------------------------------- 02712 __inline unsigned int AT91F_US_SendFrame( 02713 AT91PS_USART pUSART, 02714 char *pBuffer, 02715 unsigned int szBuffer, 02716 char *pNextBuffer, 02717 unsigned int szNextBuffer ) 02718 { 02719 return AT91F_PDC_SendFrame( 02720 (AT91PS_PDC) &(pUSART->US_RPR), 02721 pBuffer, 02722 szBuffer, 02723 pNextBuffer, 02724 szNextBuffer); 02725 } 02726 02727 //*---------------------------------------------------------------------------- 02728 //* \fn AT91F_US_ReceiveFrame 02729 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 02730 //*---------------------------------------------------------------------------- 02731 __inline unsigned int AT91F_US_ReceiveFrame ( 02732 AT91PS_USART pUSART, 02733 char *pBuffer, 02734 unsigned int szBuffer, 02735 char *pNextBuffer, 02736 unsigned int szNextBuffer ) 02737 { 02738 return AT91F_PDC_ReceiveFrame( 02739 (AT91PS_PDC) &(pUSART->US_RPR), 02740 pBuffer, 02741 szBuffer, 02742 pNextBuffer, 02743 szNextBuffer); 02744 } 02745 02746 //*---------------------------------------------------------------------------- 02747 //* \fn AT91F_US_SetIrdaFilter 02748 //* \brief Set the value of IrDa filter tregister 02749 //*---------------------------------------------------------------------------- 02750 __inline void AT91F_US_SetIrdaFilter ( 02751 AT91PS_USART pUSART, 02752 unsigned char value 02753 ) 02754 { 02755 pUSART->US_IF = value; 02756 } 02757 02758 /* ***************************************************************************** 02759 SOFTWARE API FOR TWI 02760 ***************************************************************************** */ 02761 //*---------------------------------------------------------------------------- 02762 //* \fn AT91F_TWI_EnableIt 02763 //* \brief Enable TWI IT 02764 //*---------------------------------------------------------------------------- 02765 __inline void AT91F_TWI_EnableIt ( 02766 AT91PS_TWI pTWI, // \arg pointer to a TWI controller 02767 unsigned int flag) // \arg IT to be enabled 02768 { 02769 //* Write to the IER register 02770 pTWI->TWI_IER = flag; 02771 } 02772 02773 //*---------------------------------------------------------------------------- 02774 //* \fn AT91F_TWI_DisableIt 02775 //* \brief Disable TWI IT 02776 //*---------------------------------------------------------------------------- 02777 __inline void AT91F_TWI_DisableIt ( 02778 AT91PS_TWI pTWI, // \arg pointer to a TWI controller 02779 unsigned int flag) // \arg IT to be disabled 02780 { 02781 //* Write to the IDR register 02782 pTWI->TWI_IDR = flag; 02783 } 02784 02785 //*---------------------------------------------------------------------------- 02786 //* \fn AT91F_TWI_Configure 02787 //* \brief Configure TWI in master mode 02788 //*---------------------------------------------------------------------------- 02789 __inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller 02790 { 02791 //* Disable interrupts 02792 pTWI->TWI_IDR = (unsigned int) -1; 02793 02794 //* Reset peripheral 02795 pTWI->TWI_CR = AT91C_TWI_SWRST; 02796 02797 //* Set Master mode 02798 pTWI->TWI_CR = AT91C_TWI_MSEN; 02799 02800 } 02801 02802 //*---------------------------------------------------------------------------- 02803 //* \fn AT91F_TWI_GetInterruptMaskStatus 02804 //* \brief Return TWI Interrupt Mask Status 02805 //*---------------------------------------------------------------------------- 02806 __inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status 02807 AT91PS_TWI pTwi) // \arg pointer to a TWI controller 02808 { 02809 return pTwi->TWI_IMR; 02810 } 02811 02812 //*---------------------------------------------------------------------------- 02813 //* \fn AT91F_TWI_IsInterruptMasked 02814 //* \brief Test if TWI Interrupt is Masked 02815 //*---------------------------------------------------------------------------- 02816 __inline int AT91F_TWI_IsInterruptMasked( 02817 AT91PS_TWI pTwi, // \arg pointer to a TWI controller 02818 unsigned int flag) // \arg flag to be tested 02819 { 02820 return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); 02821 } 02822 02823 /* ***************************************************************************** 02824 SOFTWARE API FOR TC 02825 ***************************************************************************** */ 02826 //*---------------------------------------------------------------------------- 02827 //* \fn AT91F_TC_InterruptEnable 02828 //* \brief Enable TC Interrupt 02829 //*---------------------------------------------------------------------------- 02830 __inline void AT91F_TC_InterruptEnable( 02831 AT91PS_TC pTc, // \arg pointer to a TC controller 02832 unsigned int flag) // \arg TC interrupt to be enabled 02833 { 02834 pTc->TC_IER = flag; 02835 } 02836 02837 //*---------------------------------------------------------------------------- 02838 //* \fn AT91F_TC_InterruptDisable 02839 //* \brief Disable TC Interrupt 02840 //*---------------------------------------------------------------------------- 02841 __inline void AT91F_TC_InterruptDisable( 02842 AT91PS_TC pTc, // \arg pointer to a TC controller 02843 unsigned int flag) // \arg TC interrupt to be disabled 02844 { 02845 pTc->TC_IDR = flag; 02846 } 02847 02848 //*---------------------------------------------------------------------------- 02849 //* \fn AT91F_TC_GetInterruptMaskStatus 02850 //* \brief Return TC Interrupt Mask Status 02851 //*---------------------------------------------------------------------------- 02852 __inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status 02853 AT91PS_TC pTc) // \arg pointer to a TC controller 02854 { 02855 return pTc->TC_IMR; 02856 } 02857 02858 //*---------------------------------------------------------------------------- 02859 //* \fn AT91F_TC_IsInterruptMasked 02860 //* \brief Test if TC Interrupt is Masked 02861 //*---------------------------------------------------------------------------- 02862 __inline int AT91F_TC_IsInterruptMasked( 02863 AT91PS_TC pTc, // \arg pointer to a TC controller 02864 unsigned int flag) // \arg flag to be tested 02865 { 02866 return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); 02867 } 02868 02869 /* ***************************************************************************** 02870 SOFTWARE API FOR PWMC 02871 ***************************************************************************** */ 02872 //*---------------------------------------------------------------------------- 02873 //* \fn AT91F_PWM_GetStatus 02874 //* \brief Return PWM Interrupt Status 02875 //*---------------------------------------------------------------------------- 02876 __inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status 02877 AT91PS_PWMC pPWM) // pointer to a PWM controller 02878 { 02879 return pPWM->PWMC_SR; 02880 } 02881 02882 //*---------------------------------------------------------------------------- 02883 //* \fn AT91F_PWM_InterruptEnable 02884 //* \brief Enable PWM Interrupt 02885 //*---------------------------------------------------------------------------- 02886 __inline void AT91F_PWMC_InterruptEnable( 02887 AT91PS_PWMC pPwm, // \arg pointer to a PWM controller 02888 unsigned int flag) // \arg PWM interrupt to be enabled 02889 { 02890 pPwm->PWMC_IER = flag; 02891 } 02892 02893 //*---------------------------------------------------------------------------- 02894 //* \fn AT91F_PWM_InterruptDisable 02895 //* \brief Disable PWM Interrupt 02896 //*---------------------------------------------------------------------------- 02897 __inline void AT91F_PWMC_InterruptDisable( 02898 AT91PS_PWMC pPwm, // \arg pointer to a PWM controller 02899 unsigned int flag) // \arg PWM interrupt to be disabled 02900 { 02901 pPwm->PWMC_IDR = flag; 02902 } 02903 02904 //*---------------------------------------------------------------------------- 02905 //* \fn AT91F_PWM_GetInterruptMaskStatus 02906 //* \brief Return PWM Interrupt Mask Status 02907 //*---------------------------------------------------------------------------- 02908 __inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status 02909 AT91PS_PWMC pPwm) // \arg pointer to a PWM controller 02910 { 02911 return pPwm->PWMC_IMR; 02912 } 02913 02914 //*---------------------------------------------------------------------------- 02915 //* \fn AT91F_PWM_IsInterruptMasked 02916 //* \brief Test if PWM Interrupt is Masked 02917 //*---------------------------------------------------------------------------- 02918 __inline unsigned int AT91F_PWMC_IsInterruptMasked( 02919 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02920 unsigned int flag) // \arg flag to be tested 02921 { 02922 return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); 02923 } 02924 02925 //*---------------------------------------------------------------------------- 02926 //* \fn AT91F_PWM_IsStatusSet 02927 //* \brief Test if PWM Interrupt is Set 02928 //*---------------------------------------------------------------------------- 02929 __inline unsigned int AT91F_PWMC_IsStatusSet( 02930 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02931 unsigned int flag) // \arg flag to be tested 02932 { 02933 return (AT91F_PWMC_GetStatus(pPWM) & flag); 02934 } 02935 02936 //*---------------------------------------------------------------------------- 02937 //* \fn AT91F_PWM_CfgChannel 02938 //* \brief Test if PWM Interrupt is Set 02939 //*---------------------------------------------------------------------------- 02940 __inline void AT91F_PWMC_CfgChannel( 02941 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02942 unsigned int channelId, // \arg PWM channel ID 02943 unsigned int mode, // \arg PWM mode 02944 unsigned int period, // \arg PWM period 02945 unsigned int duty) // \arg PWM duty cycle 02946 { 02947 pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 02948 pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; 02949 pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; 02950 } 02951 02952 //*---------------------------------------------------------------------------- 02953 //* \fn AT91F_PWM_StartChannel 02954 //* \brief Enable channel 02955 //*---------------------------------------------------------------------------- 02956 __inline void AT91F_PWMC_StartChannel( 02957 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02958 unsigned int flag) // \arg Channels IDs to be enabled 02959 { 02960 pPWM->PWMC_ENA = flag; 02961 } 02962 02963 //*---------------------------------------------------------------------------- 02964 //* \fn AT91F_PWM_StopChannel 02965 //* \brief Disable channel 02966 //*---------------------------------------------------------------------------- 02967 __inline void AT91F_PWMC_StopChannel( 02968 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02969 unsigned int flag) // \arg Channels IDs to be enabled 02970 { 02971 pPWM->PWMC_DIS = flag; 02972 } 02973 02974 //*---------------------------------------------------------------------------- 02975 //* \fn AT91F_PWM_UpdateChannel 02976 //* \brief Update Period or Duty Cycle 02977 //*---------------------------------------------------------------------------- 02978 __inline void AT91F_PWMC_UpdateChannel( 02979 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 02980 unsigned int channelId, // \arg PWM channel ID 02981 unsigned int update) // \arg Channels IDs to be enabled 02982 { 02983 pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; 02984 } 02985 02986 /* ***************************************************************************** 02987 SOFTWARE API FOR UDP 02988 ***************************************************************************** */ 02989 //*---------------------------------------------------------------------------- 02990 //* \fn AT91F_UDP_EnableIt 02991 //* \brief Enable UDP IT 02992 //*---------------------------------------------------------------------------- 02993 __inline void AT91F_UDP_EnableIt ( 02994 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 02995 unsigned int flag) // \arg IT to be enabled 02996 { 02997 //* Write to the IER register 02998 pUDP->UDP_IER = flag; 02999 } 03000 03001 //*---------------------------------------------------------------------------- 03002 //* \fn AT91F_UDP_DisableIt 03003 //* \brief Disable UDP IT 03004 //*---------------------------------------------------------------------------- 03005 __inline void AT91F_UDP_DisableIt ( 03006 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03007 unsigned int flag) // \arg IT to be disabled 03008 { 03009 //* Write to the IDR register 03010 pUDP->UDP_IDR = flag; 03011 } 03012 03013 //*---------------------------------------------------------------------------- 03014 //* \fn AT91F_UDP_SetAddress 03015 //* \brief Set UDP functional address 03016 //*---------------------------------------------------------------------------- 03017 __inline void AT91F_UDP_SetAddress ( 03018 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03019 unsigned char address) // \arg new UDP address 03020 { 03021 pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); 03022 } 03023 03024 //*---------------------------------------------------------------------------- 03025 //* \fn AT91F_UDP_EnableEp 03026 //* \brief Enable Endpoint 03027 //*---------------------------------------------------------------------------- 03028 __inline void AT91F_UDP_EnableEp ( 03029 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03030 unsigned char endpoint) // \arg endpoint number 03031 { 03032 pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; 03033 } 03034 03035 //*---------------------------------------------------------------------------- 03036 //* \fn AT91F_UDP_DisableEp 03037 //* \brief Enable Endpoint 03038 //*---------------------------------------------------------------------------- 03039 __inline void AT91F_UDP_DisableEp ( 03040 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03041 unsigned char endpoint) // \arg endpoint number 03042 { 03043 pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; 03044 } 03045 03046 //*---------------------------------------------------------------------------- 03047 //* \fn AT91F_UDP_SetState 03048 //* \brief Set UDP Device state 03049 //*---------------------------------------------------------------------------- 03050 __inline void AT91F_UDP_SetState ( 03051 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03052 unsigned int flag) // \arg new UDP address 03053 { 03054 pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); 03055 pUDP->UDP_GLBSTATE |= flag; 03056 } 03057 03058 //*---------------------------------------------------------------------------- 03059 //* \fn AT91F_UDP_GetState 03060 //* \brief return UDP Device state 03061 //*---------------------------------------------------------------------------- 03062 __inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state 03063 AT91PS_UDP pUDP) // \arg pointer to a UDP controller 03064 { 03065 return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); 03066 } 03067 03068 //*---------------------------------------------------------------------------- 03069 //* \fn AT91F_UDP_ResetEp 03070 //* \brief Reset UDP endpoint 03071 //*---------------------------------------------------------------------------- 03072 __inline void AT91F_UDP_ResetEp ( // \return the UDP device state 03073 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03074 unsigned int flag) // \arg Endpoints to be reset 03075 { 03076 pUDP->UDP_RSTEP = flag; 03077 pUDP->UDP_RSTEP = 0; 03078 } 03079 03080 //*---------------------------------------------------------------------------- 03081 //* \fn AT91F_UDP_EpStall 03082 //* \brief Endpoint will STALL requests 03083 //*---------------------------------------------------------------------------- 03084 __inline void AT91F_UDP_EpStall( 03085 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03086 unsigned char endpoint) // \arg endpoint number 03087 { 03088 pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; 03089 } 03090 03091 //*---------------------------------------------------------------------------- 03092 //* \fn AT91F_UDP_EpWrite 03093 //* \brief Write value in the DPR 03094 //*---------------------------------------------------------------------------- 03095 __inline void AT91F_UDP_EpWrite( 03096 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03097 unsigned char endpoint, // \arg endpoint number 03098 unsigned char value) // \arg value to be written in the DPR 03099 { 03100 pUDP->UDP_FDR[endpoint] = value; 03101 } 03102 03103 //*---------------------------------------------------------------------------- 03104 //* \fn AT91F_UDP_EpRead 03105 //* \brief Return value from the DPR 03106 //*---------------------------------------------------------------------------- 03107 __inline unsigned int AT91F_UDP_EpRead( 03108 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03109 unsigned char endpoint) // \arg endpoint number 03110 { 03111 return pUDP->UDP_FDR[endpoint]; 03112 } 03113 03114 //*---------------------------------------------------------------------------- 03115 //* \fn AT91F_UDP_EpEndOfWr 03116 //* \brief Notify the UDP that values in DPR are ready to be sent 03117 //*---------------------------------------------------------------------------- 03118 __inline void AT91F_UDP_EpEndOfWr( 03119 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03120 unsigned char endpoint) // \arg endpoint number 03121 { 03122 pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; 03123 } 03124 03125 //*---------------------------------------------------------------------------- 03126 //* \fn AT91F_UDP_EpClear 03127 //* \brief Clear flag in the endpoint CSR register 03128 //*---------------------------------------------------------------------------- 03129 __inline void AT91F_UDP_EpClear( 03130 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03131 unsigned char endpoint, // \arg endpoint number 03132 unsigned int flag) // \arg flag to be cleared 03133 { 03134 pUDP->UDP_CSR[endpoint] &= ~(flag); 03135 } 03136 03137 //*---------------------------------------------------------------------------- 03138 //* \fn AT91F_UDP_EpSet 03139 //* \brief Set flag in the endpoint CSR register 03140 //*---------------------------------------------------------------------------- 03141 __inline void AT91F_UDP_EpSet( 03142 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03143 unsigned char endpoint, // \arg endpoint number 03144 unsigned int flag) // \arg flag to be cleared 03145 { 03146 pUDP->UDP_CSR[endpoint] |= flag; 03147 } 03148 03149 //*---------------------------------------------------------------------------- 03150 //* \fn AT91F_UDP_EpStatus 03151 //* \brief Return the endpoint CSR register 03152 //*---------------------------------------------------------------------------- 03153 __inline unsigned int AT91F_UDP_EpStatus( 03154 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 03155 unsigned char endpoint) // \arg endpoint number 03156 { 03157 return pUDP->UDP_CSR[endpoint]; 03158 } 03159 03160 //*---------------------------------------------------------------------------- 03161 //* \fn AT91F_UDP_GetInterruptMaskStatus 03162 //* \brief Return UDP Interrupt Mask Status 03163 //*---------------------------------------------------------------------------- 03164 __inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status 03165 AT91PS_UDP pUdp) // \arg pointer to a UDP controller 03166 { 03167 return pUdp->UDP_IMR; 03168 } 03169 03170 //*---------------------------------------------------------------------------- 03171 //* \fn AT91F_UDP_IsInterruptMasked 03172 //* \brief Test if UDP Interrupt is Masked 03173 //*---------------------------------------------------------------------------- 03174 __inline int AT91F_UDP_IsInterruptMasked( 03175 AT91PS_UDP pUdp, // \arg pointer to a UDP controller 03176 unsigned int flag) // \arg flag to be tested 03177 { 03178 return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); 03179 } 03180 03181 //*---------------------------------------------------------------------------- 03182 //* \fn AT91F_DBGU_CfgPMC 03183 //* \brief Enable Peripheral clock in PMC for DBGU 03184 //*---------------------------------------------------------------------------- 03185 __inline void AT91F_DBGU_CfgPMC (void) 03186 { 03187 AT91F_PMC_EnablePeriphClock( 03188 AT91C_BASE_PMC, // PIO controller base address 03189 ((unsigned int) 1 << AT91C_ID_SYS)); 03190 } 03191 03192 //*---------------------------------------------------------------------------- 03193 //* \fn AT91F_DBGU_CfgPIO 03194 //* \brief Configure PIO controllers to drive DBGU signals 03195 //*---------------------------------------------------------------------------- 03196 __inline void AT91F_DBGU_CfgPIO (void) 03197 { 03198 // Configure PIO controllers to periph mode 03199 AT91F_PIO_CfgPeriph( 03200 AT91C_BASE_PIOA, // PIO controller base address 03201 ((unsigned int) AT91C_PA9_DRXD ) | 03202 ((unsigned int) AT91C_PA10_DTXD ), // Peripheral A 03203 0); // Peripheral B 03204 } 03205 03206 //*---------------------------------------------------------------------------- 03207 //* \fn AT91F_PMC_CfgPMC 03208 //* \brief Enable Peripheral clock in PMC for PMC 03209 //*---------------------------------------------------------------------------- 03210 __inline void AT91F_PMC_CfgPMC (void) 03211 { 03212 AT91F_PMC_EnablePeriphClock( 03213 AT91C_BASE_PMC, // PIO controller base address 03214 ((unsigned int) 1 << AT91C_ID_SYS)); 03215 } 03216 03217 //*---------------------------------------------------------------------------- 03218 //* \fn AT91F_PMC_CfgPIO 03219 //* \brief Configure PIO controllers to drive PMC signals 03220 //*---------------------------------------------------------------------------- 03221 __inline void AT91F_PMC_CfgPIO (void) 03222 { 03223 // Configure PIO controllers to periph mode 03224 AT91F_PIO_CfgPeriph( 03225 AT91C_BASE_PIOA, // PIO controller base address 03226 0, // Peripheral A 03227 ((unsigned int) AT91C_PA6_PCK0 ) | 03228 ((unsigned int) AT91C_PA18_PCK2 ) | 03229 ((unsigned int) AT91C_PA31_PCK2 ) | 03230 ((unsigned int) AT91C_PA21_PCK1 ) | 03231 ((unsigned int) AT91C_PA17_PCK1 )); // Peripheral B 03232 } 03233 03234 //*---------------------------------------------------------------------------- 03235 //* \fn AT91F_VREG_CfgPMC 03236 //* \brief Enable Peripheral clock in PMC for VREG 03237 //*---------------------------------------------------------------------------- 03238 __inline void AT91F_VREG_CfgPMC (void) 03239 { 03240 AT91F_PMC_EnablePeriphClock( 03241 AT91C_BASE_PMC, // PIO controller base address 03242 ((unsigned int) 1 << AT91C_ID_SYS)); 03243 } 03244 03245 //*---------------------------------------------------------------------------- 03246 //* \fn AT91F_RSTC_CfgPMC 03247 //* \brief Enable Peripheral clock in PMC for RSTC 03248 //*---------------------------------------------------------------------------- 03249 __inline void AT91F_RSTC_CfgPMC (void) 03250 { 03251 AT91F_PMC_EnablePeriphClock( 03252 AT91C_BASE_PMC, // PIO controller base address 03253 ((unsigned int) 1 << AT91C_ID_SYS)); 03254 } 03255 03256 //*---------------------------------------------------------------------------- 03257 //* \fn AT91F_SSC_CfgPMC 03258 //* \brief Enable Peripheral clock in PMC for SSC 03259 //*---------------------------------------------------------------------------- 03260 __inline void AT91F_SSC_CfgPMC (void) 03261 { 03262 AT91F_PMC_EnablePeriphClock( 03263 AT91C_BASE_PMC, // PIO controller base address 03264 ((unsigned int) 1 << AT91C_ID_SSC)); 03265 } 03266 03267 //*---------------------------------------------------------------------------- 03268 //* \fn AT91F_SSC_CfgPIO 03269 //* \brief Configure PIO controllers to drive SSC signals 03270 //*---------------------------------------------------------------------------- 03271 __inline void AT91F_SSC_CfgPIO (void) 03272 { 03273 // Configure PIO controllers to periph mode 03274 AT91F_PIO_CfgPeriph( 03275 AT91C_BASE_PIOA, // PIO controller base address 03276 ((unsigned int) AT91C_PA19_RK ) | 03277 ((unsigned int) AT91C_PA16_TK ) | 03278 ((unsigned int) AT91C_PA15_TF ) | 03279 ((unsigned int) AT91C_PA18_RD ) | 03280 ((unsigned int) AT91C_PA20_RF ) | 03281 ((unsigned int) AT91C_PA17_TD ), // Peripheral A 03282 0); // Peripheral B 03283 } 03284 03285 //*---------------------------------------------------------------------------- 03286 //* \fn AT91F_WDTC_CfgPMC 03287 //* \brief Enable Peripheral clock in PMC for WDTC 03288 //*---------------------------------------------------------------------------- 03289 __inline void AT91F_WDTC_CfgPMC (void) 03290 { 03291 AT91F_PMC_EnablePeriphClock( 03292 AT91C_BASE_PMC, // PIO controller base address 03293 ((unsigned int) 1 << AT91C_ID_SYS)); 03294 } 03295 03296 //*---------------------------------------------------------------------------- 03297 //* \fn AT91F_US1_CfgPMC 03298 //* \brief Enable Peripheral clock in PMC for US1 03299 //*---------------------------------------------------------------------------- 03300 __inline void AT91F_US1_CfgPMC (void) 03301 { 03302 AT91F_PMC_EnablePeriphClock( 03303 AT91C_BASE_PMC, // PIO controller base address 03304 ((unsigned int) 1 << AT91C_ID_US1)); 03305 } 03306 03307 //*---------------------------------------------------------------------------- 03308 //* \fn AT91F_US1_CfgPIO 03309 //* \brief Configure PIO controllers to drive US1 signals 03310 //*---------------------------------------------------------------------------- 03311 __inline void AT91F_US1_CfgPIO (void) 03312 { 03313 // Configure PIO controllers to periph mode 03314 AT91F_PIO_CfgPeriph( 03315 AT91C_BASE_PIOA, // PIO controller base address 03316 ((unsigned int) AT91C_PA29_RI1 ) | 03317 ((unsigned int) AT91C_PA26_DCD1 ) | 03318 ((unsigned int) AT91C_PA28_DSR1 ) | 03319 ((unsigned int) AT91C_PA27_DTR1 ) | 03320 ((unsigned int) AT91C_PA23_SCK1 ) | 03321 ((unsigned int) AT91C_PA24_RTS1 ) | 03322 ((unsigned int) AT91C_PA22_TXD1 ) | 03323 ((unsigned int) AT91C_PA21_RXD1 ) | 03324 ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A 03325 0); // Peripheral B 03326 } 03327 03328 //*---------------------------------------------------------------------------- 03329 //* \fn AT91F_US0_CfgPMC 03330 //* \brief Enable Peripheral clock in PMC for US0 03331 //*---------------------------------------------------------------------------- 03332 __inline void AT91F_US0_CfgPMC (void) 03333 { 03334 AT91F_PMC_EnablePeriphClock( 03335 AT91C_BASE_PMC, // PIO controller base address 03336 ((unsigned int) 1 << AT91C_ID_US0)); 03337 } 03338 03339 //*---------------------------------------------------------------------------- 03340 //* \fn AT91F_US0_CfgPIO 03341 //* \brief Configure PIO controllers to drive US0 signals 03342 //*---------------------------------------------------------------------------- 03343 __inline void AT91F_US0_CfgPIO (void) 03344 { 03345 // Configure PIO controllers to periph mode 03346 AT91F_PIO_CfgPeriph( 03347 AT91C_BASE_PIOA, // PIO controller base address 03348 ((unsigned int) AT91C_PA5_RXD0 ) | 03349 ((unsigned int) AT91C_PA8_CTS0 ) | 03350 ((unsigned int) AT91C_PA7_RTS0 ) | 03351 ((unsigned int) AT91C_PA6_TXD0 ), // Peripheral A 03352 ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B 03353 } 03354 03355 //*---------------------------------------------------------------------------- 03356 //* \fn AT91F_SPI_CfgPMC 03357 //* \brief Enable Peripheral clock in PMC for SPI 03358 //*---------------------------------------------------------------------------- 03359 __inline void AT91F_SPI_CfgPMC (void) 03360 { 03361 AT91F_PMC_EnablePeriphClock( 03362 AT91C_BASE_PMC, // PIO controller base address 03363 ((unsigned int) 1 << AT91C_ID_SPI)); 03364 } 03365 03366 //*---------------------------------------------------------------------------- 03367 //* \fn AT91F_SPI_CfgPIO 03368 //* \brief Configure PIO controllers to drive SPI signals 03369 //*---------------------------------------------------------------------------- 03370 __inline void AT91F_SPI_CfgPIO (void) 03371 { 03372 // Configure PIO controllers to periph mode 03373 AT91F_PIO_CfgPeriph( 03374 AT91C_BASE_PIOA, // PIO controller base address 03375 ((unsigned int) AT91C_PA13_MOSI ) | 03376 ((unsigned int) AT91C_PA31_NPCS1 ) | 03377 ((unsigned int) AT91C_PA14_SPCK ) | 03378 ((unsigned int) AT91C_PA11_NPCS0 ) | 03379 ((unsigned int) AT91C_PA12_MISO ), // Peripheral A 03380 ((unsigned int) AT91C_PA9_NPCS1 ) | 03381 ((unsigned int) AT91C_PA22_NPCS3 ) | 03382 ((unsigned int) AT91C_PA3_NPCS3 ) | 03383 ((unsigned int) AT91C_PA5_NPCS3 ) | 03384 ((unsigned int) AT91C_PA10_NPCS2 ) | 03385 ((unsigned int) AT91C_PA30_NPCS2 )); // Peripheral B 03386 } 03387 03388 //*---------------------------------------------------------------------------- 03389 //* \fn AT91F_PITC_CfgPMC 03390 //* \brief Enable Peripheral clock in PMC for PITC 03391 //*---------------------------------------------------------------------------- 03392 __inline void AT91F_PITC_CfgPMC (void) 03393 { 03394 AT91F_PMC_EnablePeriphClock( 03395 AT91C_BASE_PMC, // PIO controller base address 03396 ((unsigned int) 1 << AT91C_ID_SYS)); 03397 } 03398 03399 //*---------------------------------------------------------------------------- 03400 //* \fn AT91F_AIC_CfgPMC 03401 //* \brief Enable Peripheral clock in PMC for AIC 03402 //*---------------------------------------------------------------------------- 03403 __inline void AT91F_AIC_CfgPMC (void) 03404 { 03405 AT91F_PMC_EnablePeriphClock( 03406 AT91C_BASE_PMC, // PIO controller base address 03407 ((unsigned int) 1 << AT91C_ID_FIQ) | 03408 ((unsigned int) 1 << AT91C_ID_IRQ0) | 03409 ((unsigned int) 1 << AT91C_ID_IRQ1)); 03410 } 03411 03412 //*---------------------------------------------------------------------------- 03413 //* \fn AT91F_AIC_CfgPIO 03414 //* \brief Configure PIO controllers to drive AIC signals 03415 //*---------------------------------------------------------------------------- 03416 __inline void AT91F_AIC_CfgPIO (void) 03417 { 03418 // Configure PIO controllers to periph mode 03419 AT91F_PIO_CfgPeriph( 03420 AT91C_BASE_PIOA, // PIO controller base address 03421 ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A 03422 ((unsigned int) AT91C_PA20_IRQ0 ) | 03423 ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B 03424 } 03425 03426 //*---------------------------------------------------------------------------- 03427 //* \fn AT91F_TWI_CfgPMC 03428 //* \brief Enable Peripheral clock in PMC for TWI 03429 //*---------------------------------------------------------------------------- 03430 __inline void AT91F_TWI_CfgPMC (void) 03431 { 03432 AT91F_PMC_EnablePeriphClock( 03433 AT91C_BASE_PMC, // PIO controller base address 03434 ((unsigned int) 1 << AT91C_ID_TWI)); 03435 } 03436 03437 //*---------------------------------------------------------------------------- 03438 //* \fn AT91F_TWI_CfgPIO 03439 //* \brief Configure PIO controllers to drive TWI signals 03440 //*---------------------------------------------------------------------------- 03441 __inline void AT91F_TWI_CfgPIO (void) 03442 { 03443 // Configure PIO controllers to periph mode 03444 AT91F_PIO_CfgPeriph( 03445 AT91C_BASE_PIOA, // PIO controller base address 03446 ((unsigned int) AT91C_PA4_TWCK ) | 03447 ((unsigned int) AT91C_PA3_TWD ), // Peripheral A 03448 0); // Peripheral B 03449 } 03450 03451 //*---------------------------------------------------------------------------- 03452 //* \fn AT91F_PWMC_CH3_CfgPIO 03453 //* \brief Configure PIO controllers to drive PWMC_CH3 signals 03454 //*---------------------------------------------------------------------------- 03455 __inline void AT91F_PWMC_CH3_CfgPIO (void) 03456 { 03457 // Configure PIO controllers to periph mode 03458 AT91F_PIO_CfgPeriph( 03459 AT91C_BASE_PIOA, // PIO controller base address 03460 0, // Peripheral A 03461 ((unsigned int) AT91C_PA7_PWM3 ) | 03462 ((unsigned int) AT91C_PA14_PWM3 )); // Peripheral B 03463 } 03464 03465 //*---------------------------------------------------------------------------- 03466 //* \fn AT91F_PWMC_CH2_CfgPIO 03467 //* \brief Configure PIO controllers to drive PWMC_CH2 signals 03468 //*---------------------------------------------------------------------------- 03469 __inline void AT91F_PWMC_CH2_CfgPIO (void) 03470 { 03471 // Configure PIO controllers to periph mode 03472 AT91F_PIO_CfgPeriph( 03473 AT91C_BASE_PIOA, // PIO controller base address 03474 ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A 03475 ((unsigned int) AT91C_PA13_PWM2 ) | 03476 ((unsigned int) AT91C_PA25_PWM2 )); // Peripheral B 03477 } 03478 03479 //*---------------------------------------------------------------------------- 03480 //* \fn AT91F_PWMC_CH1_CfgPIO 03481 //* \brief Configure PIO controllers to drive PWMC_CH1 signals 03482 //*---------------------------------------------------------------------------- 03483 __inline void AT91F_PWMC_CH1_CfgPIO (void) 03484 { 03485 // Configure PIO controllers to periph mode 03486 AT91F_PIO_CfgPeriph( 03487 AT91C_BASE_PIOA, // PIO controller base address 03488 ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A 03489 ((unsigned int) AT91C_PA24_PWM1 ) | 03490 ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B 03491 } 03492 03493 //*---------------------------------------------------------------------------- 03494 //* \fn AT91F_PWMC_CH0_CfgPIO 03495 //* \brief Configure PIO controllers to drive PWMC_CH0 signals 03496 //*---------------------------------------------------------------------------- 03497 __inline void AT91F_PWMC_CH0_CfgPIO (void) 03498 { 03499 // Configure PIO controllers to periph mode 03500 AT91F_PIO_CfgPeriph( 03501 AT91C_BASE_PIOA, // PIO controller base address 03502 ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A 03503 ((unsigned int) AT91C_PA23_PWM0 ) | 03504 ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B 03505 } 03506 03507 //*---------------------------------------------------------------------------- 03508 //* \fn AT91F_ADC_CfgPMC 03509 //* \brief Enable Peripheral clock in PMC for ADC 03510 //*---------------------------------------------------------------------------- 03511 __inline void AT91F_ADC_CfgPMC (void) 03512 { 03513 AT91F_PMC_EnablePeriphClock( 03514 AT91C_BASE_PMC, // PIO controller base address 03515 ((unsigned int) 1 << AT91C_ID_ADC)); 03516 } 03517 03518 //*---------------------------------------------------------------------------- 03519 //* \fn AT91F_ADC_CfgPIO 03520 //* \brief Configure PIO controllers to drive ADC signals 03521 //*---------------------------------------------------------------------------- 03522 __inline void AT91F_ADC_CfgPIO (void) 03523 { 03524 // Configure PIO controllers to periph mode 03525 AT91F_PIO_CfgPeriph( 03526 AT91C_BASE_PIOA, // PIO controller base address 03527 0, // Peripheral A 03528 ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B 03529 } 03530 03531 //*---------------------------------------------------------------------------- 03532 //* \fn AT91F_RTTC_CfgPMC 03533 //* \brief Enable Peripheral clock in PMC for RTTC 03534 //*---------------------------------------------------------------------------- 03535 __inline void AT91F_RTTC_CfgPMC (void) 03536 { 03537 AT91F_PMC_EnablePeriphClock( 03538 AT91C_BASE_PMC, // PIO controller base address 03539 ((unsigned int) 1 << AT91C_ID_SYS)); 03540 } 03541 03542 //*---------------------------------------------------------------------------- 03543 //* \fn AT91F_UDP_CfgPMC 03544 //* \brief Enable Peripheral clock in PMC for UDP 03545 //*---------------------------------------------------------------------------- 03546 __inline void AT91F_UDP_CfgPMC (void) 03547 { 03548 AT91F_PMC_EnablePeriphClock( 03549 AT91C_BASE_PMC, // PIO controller base address 03550 ((unsigned int) 1 << AT91C_ID_UDP)); 03551 } 03552 03553 //*---------------------------------------------------------------------------- 03554 //* \fn AT91F_TC0_CfgPMC 03555 //* \brief Enable Peripheral clock in PMC for TC0 03556 //*---------------------------------------------------------------------------- 03557 __inline void AT91F_TC0_CfgPMC (void) 03558 { 03559 AT91F_PMC_EnablePeriphClock( 03560 AT91C_BASE_PMC, // PIO controller base address 03561 ((unsigned int) 1 << AT91C_ID_TC0)); 03562 } 03563 03564 //*---------------------------------------------------------------------------- 03565 //* \fn AT91F_TC0_CfgPIO 03566 //* \brief Configure PIO controllers to drive TC0 signals 03567 //*---------------------------------------------------------------------------- 03568 __inline void AT91F_TC0_CfgPIO (void) 03569 { 03570 // Configure PIO controllers to periph mode 03571 AT91F_PIO_CfgPeriph( 03572 AT91C_BASE_PIOA, // PIO controller base address 03573 0, // Peripheral A 03574 ((unsigned int) AT91C_PA0_TIOA0 ) | 03575 ((unsigned int) AT91C_PA4_TCLK0 ) | 03576 ((unsigned int) AT91C_PA1_TIOB0 )); // Peripheral B 03577 } 03578 03579 //*---------------------------------------------------------------------------- 03580 //* \fn AT91F_TC1_CfgPMC 03581 //* \brief Enable Peripheral clock in PMC for TC1 03582 //*---------------------------------------------------------------------------- 03583 __inline void AT91F_TC1_CfgPMC (void) 03584 { 03585 AT91F_PMC_EnablePeriphClock( 03586 AT91C_BASE_PMC, // PIO controller base address 03587 ((unsigned int) 1 << AT91C_ID_TC1)); 03588 } 03589 03590 //*---------------------------------------------------------------------------- 03591 //* \fn AT91F_TC1_CfgPIO 03592 //* \brief Configure PIO controllers to drive TC1 signals 03593 //*---------------------------------------------------------------------------- 03594 __inline void AT91F_TC1_CfgPIO (void) 03595 { 03596 // Configure PIO controllers to periph mode 03597 AT91F_PIO_CfgPeriph( 03598 AT91C_BASE_PIOA, // PIO controller base address 03599 0, // Peripheral A 03600 ((unsigned int) AT91C_PA15_TIOA1 ) | 03601 ((unsigned int) AT91C_PA28_TCLK1 ) | 03602 ((unsigned int) AT91C_PA16_TIOB1 )); // Peripheral B 03603 } 03604 03605 //*---------------------------------------------------------------------------- 03606 //* \fn AT91F_TC2_CfgPMC 03607 //* \brief Enable Peripheral clock in PMC for TC2 03608 //*---------------------------------------------------------------------------- 03609 __inline void AT91F_TC2_CfgPMC (void) 03610 { 03611 AT91F_PMC_EnablePeriphClock( 03612 AT91C_BASE_PMC, // PIO controller base address 03613 ((unsigned int) 1 << AT91C_ID_TC2)); 03614 } 03615 03616 //*---------------------------------------------------------------------------- 03617 //* \fn AT91F_TC2_CfgPIO 03618 //* \brief Configure PIO controllers to drive TC2 signals 03619 //*---------------------------------------------------------------------------- 03620 __inline void AT91F_TC2_CfgPIO (void) 03621 { 03622 // Configure PIO controllers to periph mode 03623 AT91F_PIO_CfgPeriph( 03624 AT91C_BASE_PIOA, // PIO controller base address 03625 0, // Peripheral A 03626 ((unsigned int) AT91C_PA27_TIOB2 ) | 03627 ((unsigned int) AT91C_PA26_TIOA2 ) | 03628 ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B 03629 } 03630 03631 //*---------------------------------------------------------------------------- 03632 //* \fn AT91F_MC_CfgPMC 03633 //* \brief Enable Peripheral clock in PMC for MC 03634 //*---------------------------------------------------------------------------- 03635 __inline void AT91F_MC_CfgPMC (void) 03636 { 03637 AT91F_PMC_EnablePeriphClock( 03638 AT91C_BASE_PMC, // PIO controller base address 03639 ((unsigned int) 1 << AT91C_ID_SYS)); 03640 } 03641 03642 //*---------------------------------------------------------------------------- 03643 //* \fn AT91F_PIOA_CfgPMC 03644 //* \brief Enable Peripheral clock in PMC for PIOA 03645 //*---------------------------------------------------------------------------- 03646 __inline void AT91F_PIOA_CfgPMC (void) 03647 { 03648 AT91F_PMC_EnablePeriphClock( 03649 AT91C_BASE_PMC, // PIO controller base address 03650 ((unsigned int) 1 << AT91C_ID_PIOA)); 03651 } 03652 03653 //*---------------------------------------------------------------------------- 03654 //* \fn AT91F_PWMC_CfgPMC 03655 //* \brief Enable Peripheral clock in PMC for PWMC 03656 //*---------------------------------------------------------------------------- 03657 __inline void AT91F_PWMC_CfgPMC (void) 03658 { 03659 AT91F_PMC_EnablePeriphClock( 03660 AT91C_BASE_PMC, // PIO controller base address 03661 ((unsigned int) 1 << AT91C_ID_PWMC)); 03662 } 03663 03664 #endif // lib_AT91SAM7S64_H
1.5.9